Introduction
Hello, my name is Masuo.
This blush episode is about what I thought when I first learned about FPGA's internal memory block.
There is a memory block (= a dedicated area used as memory) built into the FPGA device.
Figure 1. Internal Structure of Cyclone® IV
The user can realize the following three types of memory in this memory block
RAM (Random Access Memory): Memory that can write and read data to and from a specified address. It is volatile and erases data when the power is turned off.
･ROM (Read Only Memory): Memory that reads out data at a specified address. It is non-volatile and data remains even when the power is turned off. It is necessary to write data in ROM in advance.
･FIFO (First-In First-Out): Memory that reads out the written data in the order of oldest to newest. There is no concept of address.
Memory blocks can be designed from the Quartus® II Tools menu ⇒ MegaWizard Plug-In Manager.
I wondered how an FPGA memory block could realize three types of memory ( ROM, RAM, and FIFO ).
Here, Masuo had an epiphany: "ROM can be powered off and the FIFO can be powered on.
ROM does not lose data even if the power is turned off. If this is the case, we can realize the ROM in the memory block of the FPGA and write circuit data to it. Couldn't we use the memory block as a configuration memory?"
Figure 2: Masuo's blushing image
I told the senior employee about Mas-man's idea.
Senior employee: "FPGAs are SRAM structures and are volatile, meaning that data is lost when the power is turned off. Similarly, the internal memory block is also an SRAM structure. The physical structure of the memory block does not change to a ROM structure (laughs)."
In other words, the internal memory block was an SRAM structure, and it operated (behaved) like a ROM or FIFO by freely programming whether the Write Enable and Address signals were connected or not!
･SRAM without write signal (Write Enable) works like ROM.
･SRAM without address signal (Address) behaves like a FIFO.
Masuo "I mistakenly thought that the physical structure of the memory block changes (shame). The real appeal of FPGAs is that we can freely program whether or not to connect the control signals of the memory! The configuration device is a non-volatile ROM, so it can't be an SRAM memory block, can it?"
Senior employee: "It is not correct to say that ROM can be used for configuration. Do you know that ROM has various physical structures? Look up the different types of memory."
Figure 3: Types of memory
Masuo - "So the device for configuration is a flash ROM structure!"
What we learned
･Altera FPGA's internal memory block can realize RAM, ROM, and FIFO.
･The internal memory block is an SRAM structure, and can be programmed to operate like a ROM or FIFO by freely connecting or disconnecting the Write Enable and Address signals.
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