Hello, my name is Taro.
In this article, I will explain the relationship between PLL loop bandwidth and spread spectrum.
For more information about PLL and spread spectrum, please refer to my previous column.
The following pages are related to this article.
About Buffers
I wrote about the difference between Zero Delay Buffer and Fanout Buffer is the presence or absence of PLL.
Basic structure of PLL is also described in this article.
PLL frequency divider / multiplier
I wrote about the principle of frequency division and multiplication by PLL.
The principle of spread spectrum clock generation is based on PLL frequency division/multiplication.
PLL Applications (Reduce EMI by Spread Spectrum!)
I wrote about the purpose and principles of clock spectrum spreading, as well as the precautions when using spread spectrum clocks.
What is the loop bandwidth of a PLL?
The loop bandwidth of a PLL is determined by the loop filter (LPF), which is a component of the PLL.
Since the LPF is really a low-pass filter, it outputs low frequency bands and cuts high frequency bands.
The point where the LPF cuts the high frequency band (with a gain of -3 dB) is called the cut-off frequency The frequency band up to the cutoff frequency is called the loop frequency.
The frequency band up to the cutoff frequency is called the loop bandwidth.
When the loop bandwidth of the PLL is narrow
A narrower loop bandwidth slows down the response of the VCO output to the PFD/CP.
Although the PLL lock time (the time it takes for the REF and FB to synchronize) will increase, the instantaneous phase/frequency change of the signal can be ignored.
In other words, the Jitter can be compressed.
To compress the Jitter, the loop bandwidth must be narrowed.
When the PLL loop bandwidth is wide
When the loop bandwidth is set wide, the response of the VCO output to the PFD/CP becomes faster.
Therefore, the PLL lock time will be shorter and the frequency division/multiplication response will be faster.
The loop bandwidth of the PLL in a clock generator that uses the crystal output as REF must be set wide.
However, since Jitter compression of the REF signal cannot be expected, it is recommended to use a crystal with as high a frequency precision as possible for the clock generator.
Loop Bandwidth and Spread Spectrum
As explained in the previous article, spread spectrum reduces EMI by varying the output frequency.
Because of the need to vary the frequency, the response to changing the output frequency must be fast.
In other words, the loop bandwidth must be wide when spread spectrum is applied to a clock signal.
Thus, when applying spread spectrum, the loop bandwidth must also be taken into account.
When distributing the spread spectrum clock signal through the Zero Delay Buffer (ZDB), the loop bandwidth of the PLL inside the ZDB must be considered.
IDT's PCI Express buffers have a wide/narrow loop bandwidth setting via pin input, allowing for both output Jitter reduction and spread-spectrum clock signal distribution.
In addition, Fanout Mode and ZDB Mode can be selected to suit the customer's design.
We have other buffer products with various functions and features, so please feel free to contact us for more information!
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