Hello, my name is Wrinkle, and I am gaining knowledge through training every day.
In my last article, I wrote about "Processing DDR data with FPGA".
Reading it again, I wondered what part of the FPGA does the conversion from DDR to SDR?
This raised a new question: "What part of the FPGA does the DDR to SDR conversion take place?
Wrinkled "In which part of the FPGA is the DDR to SDR conversion process taking place?"
Senior "The conversion is done in the I/O part of the memory IP.
I/O stands for "Input/Output" and literally means the part that performs input/output.
Figure 1 FPGA and memory interface
It is true that the data cannot be processed unless it is converted into a form that can be processed inside the FPGA at the input/output part.
However, another question arose.
What is memory IP?
So this time, I decided to look into memory IP.
What is IP?
In order to investigate memory IP, I first reviewed IP.
When I first heard the word IP, I associated it with IP (Internet Protocol) for IP address, but IP here stands for Intellectual Property, which directly translates to "intellectual property.
What is intellectual property? But to put it simply, IP refers to "a functional circuit block that has already been designed.
As the scale of circuits increases, designing all circuit blocks from scratch requires a lot of man-hours.
However, by using existing design information (IP) for each functional block used in FPGA design, such as CPUs and memory controllers, it is possible to design FPGAs easily.
For a complete list of Intel/Partner IP, please visit Intel's Find IP page.
What is Memory IP?
Memory IP is the circuitry that controls DDR memory and has the following two general roles
- Accurately transfer data between FPGA and memory
- Efficiently transfer data between FPGA and memory
The block diagram of a memory IP is shown in the blue box in Figure 2.
It also consists of four major components as shown in Table 1.
The roles of each component of the memory IP are shown in Figure 2 and Table 1.
Figure 2: Block Diagram of FPGA-Memory Interface and Memory IP
Table 1: Components of Memory IP
After the FPGA is booted, the memory IP performs the following operations before it is ready to read/write from the user circuitry to the DDR memory.
- The memory controller initializes the memory while the PHY performs calibration.
- After calibration, the user can control the memory controller.
- The MPFE selects the user circuitry and the memory controller issues read/write commands.
- The issued commands are transferred through the PHY and I/O, and the associated data transfer is performed on the I/O according to the memory standard.
While IP makes it easy to design FPGAs, it is difficult to debug bugs if you do not know the internals.
This article on memory IP has helped me to understand the role of each element of memory IP, which will be useful for debugging bugs and creating memory IP that can transfer data more efficiently.
Conclusion
- IPs are pre-designed functional circuit blocks that can be reused and easily used to design FPGAs.
- Memory IPs are circuits that control DDR memory and are responsible for accurate and efficient data transfer.
- Memory IP consists of MPFE, memory controller, PHY, and I/O. DDR to SDR conversion is done in the I/O part.
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