Hello, this is Shiwshiw.
In this article, I would like to explain the FPGA selection process and methods that are required before generating memory IP.
In my previous article, " Memory IP ~ accurate and efficient data transfer", I wrote about the configuration of memory IP, which is a circuit that controls DDR memory.
I thought, "Now that we know what constitutes memory IP, let's generate memory IP!" So, I launched the "IP Catalog" from Quartus® Prime's "Tools" to select the memory IPs I wanted to generate.
When I tried to select which memory IP to generate, I got the following error message,
Shiwshiw: "Hey, I think there are other types of memory IPs besides DDR2, DDR3, and LPDDR2..."
So, this time, we will talk about FPGA selection, which must be done before memory IP generation.
FPGA Selection
To generate memory IP, it is necessary to know which FPGA family supports which memory.
This is where the EMIF Spec Estimator tool comes in handy.
The EMIF Spec Estimator is a tool that allows you to select FPGAs according to their memory specifications.
Using this tool, the memory interface performance of each device can be determined.
I also tried to find a list that would allow me to quickly see which FPGAs support which memory types.
If you go to the External Memory Interface page of Altera's website and click on "Device Support," you will find a table that lists the External Memory Interface Support Device Memory Type and the Memory Type of each device. The table below shows the external memory interface support device memory type.
The table below shows the FPGA family on the vertical axis and the memory type on the horizontal axis.
（The numbers in the table indicate the maximum operating frequency and maximum data transfer rate of each memory type for each FPGA family.
Since the maximum operating frequency is fixed for each FPGA family and memory type, the maximum operating frequency varies depending on the device even when the same memory is used.
For example, for DDR3 memory, Stratix® V has a maximum operating frequency of 933 MHz, while Stratix® 10 has a maximum operating frequency of 1066 MHz.
In this case, Cyclone® V was selected for my project.
Looking at the Cyclone® V section, I found that RLDRAM and QDR are not supported, but LPDDR2, DDR2, and DDR3 are supported.
Now that we know how to select which FPGA supports which memory in this article, we will write about how to generate memory IP in the next article.
Summary
- FPGA selection methods include EMIF Spec Estimator and External Memory Interface Support Device Memory Type.
- EMIF Spec Estimator is effective for those who want to search detailed information such as I/O standards, clock rates, and interface types.
- External Memory Interface Support Device Memory Type is available for those who want to know at a glance the maximum operating frequency of each device and which devices support which memory types.
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