Verilog HDL

Verilog HDL

Hardware languages are required to design hardware. It is like the C language for software.
Of course, it is also necessary when designing FPGAs.

There are different types of languages such as Verilog HDL, VHDL, System verilog, etc. This time, we will introduce Verilog HDL.
The first stumbling block I encountered when learning Verilog HDL during the training was the difference between procedural assignment statements and continuous assignment statements. The differences are as follows.

• Procedural assignment statement: Flip-flop ( FF ) is used to temporarily hold data.
• Continuous assignment statement: Used when the combinational circuit wants to output data. For example, if and case statements hold data and then output.

I didn't understand what was written in this way, so I asked my seniors and they told me that in digital circuits there are only two types: combinational circuits and FFs.

According to the grammar, the always statement can describe both FF and combinational circuits, while the assign statement describes only combinational circuits.

So, how does one distinguish between FF and combinational circuits in the always statement?

The distinction is made in the sensitivity list.

If there is a description of a clock in the sensitivity list, it is a circuit using FF, and if there is an input/output other than a clock in the sensitivity list, it is a description of a combinational circuit.

It is difficult to understand even if it is written only in words, so I confirmed it with an actual description example and RTL Viewer.

Here is the description of the continuous assignment statement and RTL Viewer.

The left side is the case where the always statement is used, and the right side is the case where the assign statement is used.

Next, here is the description of the procedural assignment statement and RTL Viewer.

You can certainly see the difference between FF and combinational circuits at a glance.

RTL Viewer is really useful!

Even for a simple circuit like this, it is necessary to clarify for yourself whether you want to build a FF or a combinational circuit, which is what I learned this time.

Recommended articles/documents

• Altera FPGA Development Flow / FPGA Top Page
• Verilog HDL
• Verilog HDL : Difference between Blocking and Non-blocking Logic Synthesis
• Difference between Verilog HDL and VHDL - Struggles in Conversion
• Difference between VHDL and Verilog HDL - signals with different bit widths

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