Hello. This is Totto.
Some of you may look at the title of this column and think, "Huh? You may be thinking, "What's that?
Actually, there was a continuation of this column, " Difference between Synchronous and Asynchronous Circuits ".
Synopsis
After finishing the previous column, I told my senior, "I understand that FPGAs should be designed with synchronous circuits,
Me: "Sixteen."
Senior: "If it were a 17-bit counter, how many LEs do you think it would consume? "
Me: "LE consists of a 4-input 1-output LUT and a register, so... 17?"
Senpai: "30 points! Try to make a 17 bit counter in both schematic and language."
I made a 17-bit counter and checked it.
As before, I made a 17-bit synchronous counter in the schematic and checked the compile report.
Me: "Huh? It consumes 23 LEs..."
I wondered why, and found the answer in my words earlier.
As the number of bits in a synchronous counter increases, the number of input ports for and elements increases, so one LUT for one counter is not enough to compensate for the increase.
For more information on LUTs, please refer to Ume Onigiri's "What's an FPGA? What is an FPGA?
Therefore, 23 LEs of Cyclone ® IV E are consumed.
I made a 17-bit counter in the Cyclone ® IV E language and checked the compile report.
The 17-bit synchronous counter in Cyclone ® IV E consumes 17 LEs.
Why? I wondered,
I compared the two Resource Property Editors.
Comparison of 17-bit synchronous counter in schematic and 17-bit synchronous counter in language
Comparing the 17-bit synchronous counter in the schematic with the inside of the LE of the 17-bit synchronous counter in the language
･The 17-bit synchronous counter in the schematic does not use the Carry Chain.
･The 17-bit synchronous counter in the language uses the Carry Chain.
*Carry Chain is a dedicated wiring that connects adjacent LEs to realize high-speed operations such as counters and adders.*
*Conditions under which Carry Chain is used: 1. Counter design in language 2. Design using LPM counters from Altera MegaFunction*
We found that the 17-bit synchronous counter in the language does not consume extra LE because it uses Carry Chain.
We also understood that the synchronous circuit design is suitable for FPGA design because it can reduce LE consumption by using the Carry Chain in the LE architecture.
Summary of this study
･The LE architecture includes the Carry Chain.
･Synchronous circuit design in FPGAs can reduce LE consumption.
Back to the comparison (first article)...
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