Hi, this is Tot.
In the previous comparison section, the non-periodic counter did not change all bits at the same time. Why don't all bits change at the same time?
Why all bits do not change at the same time?
The cause is that the input clock edges of each register are different.
The time required for each register to reach the clock input is different.
- Clock delay to register 1 = routing delay from the input clock pin
- Clock delay to register 2 = tco + routing delay of register 1
- Clock delay to register 3 = tco of register 2 + routing delay
tco is the time from clock in to register to data out.
The tco of each register is a fixed value depending on the device.
RoutinRouting Delay
Figure 2 below shows the internal structure of an FPGA device.
Where the asynchronous counter (Figure 1) circuitry is placed on the FPGA device and which wires are used depends on the compilation.
In an asynchronous counter, the output of one register is the clock for the next register, so the clock delay depends on the wiring.
This is the reason why the asynchronous counter changes data at different times for each bit.
Next time, we will discuss the conclusion.
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