Hello. This is Ume Onigiri.
In the last issue, we succeeded in reducing the configuration time in AS mode by compressing the size of configuration data.
However, greedy Ume Onigiri was wondering "if it is possible to shorten the configuration time even more."
After much searching, he found a configuration mode with a name that sounded very fast.
Fast Passive Parallel (FPP) mode!
Let's take a look at how much configuration time can be reduced in FPP mode.
FPP Mode
FPP mode consists of the following configuration.
For annotations in the figure, please refer to the Cyclone IV documentation.
There are two differences from the previous AS mode.
The first is that the width of the configuration data is 8 bits.
Compared to the 1-bit configuration in AS mode, the configuration is completed in 1/8 of the number of clocks.
Second, the Cyclone® IV E receives the clock for configuration.
In AS mode, the oscillator inside the FPGA was used, but by inserting an external clock, the data transfer can be done with a faster clock.
A question arose here.
"Is there an upper limit to the speed of the data transfer clock?"
Checking the data sheet, it seems that the upper limit can be up to 133MHz (66MHz for Cyclone IV E with a core voltage of 1.0V).
Compared to the data transfer clock of 20 to 40 MHz in AS mode, it seems that it can be considerably faster.
Now let's do the actual calculation.
The following formula is calculated assuming that DCLK is 133MHz (7.5ns).
Data size × DCLK period / Data width
(2,944,088 bits × 7.5 ns ) ÷ 8 bits = 2.7 ms
In AS mode, the data width is 33.1 to 95.6 ms even after compression, whereas in FPP mode, the data width is 2.7 ms.
In FPP mode, the data width was significantly reduced to 2.7 ms.
Conclusion
The FPP mode has significantly reduced the configuration time.
Ume Onigiri thought it would be impossible to reduce the configuration time any further.
However, considering the time it takes for the device to enter user mode after power is turned on
There is still a way to shorten the time.
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