Hello, this is Masuo.
In the previous article, " To operate PLL accurately (1) ", I introduced that there are some wirings that optimize the PLL phase alignment and others that do not compensate for phase alignment.
Using the Cyclone® IV E as an example, we will introduce design guidelines for driving the PLL directly from the dedicated pins!
The following two points should be noted in the design
Note 1: Designs that use a single clock signal to drive multiple PLLs
As shown in Figure 1-1, a design that drives multiple PLLs with a single clock signal will result in a "Global Clock" in the Fitter Report and may generate a Critical Warning.
In other words, the phase adjustment will not be compensated as described in the previous section.
Figure 1-1: Design with 4 PLLs driven by a single clock signal
Figure 1-2: Wiring Architecture
Figure 1-2 shows that PLL_3 and PLL_2 can be driven directly by the CLK [8] pin, but PLL_1 and PLL_4 cannot be driven directly, so they must be routed through the Global Control Bock (Figure 1-3).
Figure 1-3: Part of Compilation Report PLL Summary
Note 2: Clock Signal Pin Assignment
To avoid going through the Global Control Block, we changed the design Figure 1-1 so that the clock signal and PLL are one-to-one (Figure 2-1).
However, depending on the clock signal pin assignment, the Fitter report may show "Global Clock" and a critical warning may occur.
Figure 2-1: Design with one-to-one clock signal and PLL
￭ Pin assignment via Global Clock (Critical Warning)
As shown in Figure 2-2, four clock signals are placed on CLK [8] to CLK [11] pins.
CLK [8] to CLK [11] pins share the wiring area where PLL_3 and PLL_2 can be driven directly.
PLL_1 and PLL_4 have no wiring area where they can be driven directly, Therefore, they are routed through the Global Control Block (Figure 2-3).
Figure 2-2: Pin Assignment
Figure 2-3 Part of PLL Summary of Compilation Report
￭ Pin assignment via Dedicated Pin (optimal)
As shown in Figure 2-4, four clock signals are placed on the CLK [1], CLK [8], CLK [4], and CLK [12] pins.
Each of them drives the PLL directly from the Dedicated Pin (Figure 2-5).
Figure 2-4: Pin Assignment
Figure 2-5: Part of PLL Summary of Compilation Report
￭ Pin assignment via Dedicated Pin ( Warning )
So far, we have discussed that "If all Inclk* signal type columns in the Compilation Report PLL Summary show "Dedicated Pin", it is OK! However, the report does not show "Dedicated Pin".
However, there are wirings in Cyclone IV E for which phase adjustment is not compensated even though the report shows Dedicated Pin (confusing...). See Remarks column (3) in the
Handbook (Figure 2-6).
Figure 2-6: Wiring Architecture
Two inputs are available to drive the PLL
･Dedicated Pin
･Global Clock
The Dedicated Pin can drive the PLL directly, but there are three types depending on the relationship between the pin and the PLL.
The table below summarizes the three types.
If phase compensation is not required, the PLL can be used without concern.
If compensation for phase adjustment is required, check the positional relationship between the clock input pin and PLL.
Figure 2-7: Relationship of Wiring Area and Pin Assignment between PLLs
We now understand that it is important to consider the relationship between the CLK [*] pin and the wiring area between the PLLs in pin placement.
Conclusion
If compensation for phase adjustment by the PLL is required, check the clock routing architecture diagram from the Handbook of the device to be designed and place pins on the CLK [*] of the wiring that can directly drive the PLL.
The above is an introduction to FPGA design for optimizing PLL phase adjustment.
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