1. Introduction
This "Getting Started with SoC" series of technical contents is intended for novice users of Altera® (Intel®) SoC FPGAs.
SoC FPGAs are bus-connected within the device between the Arm® Cortex®-A9 MPCore processor and the FPGA. This intra-device connection is expected to solve the transfer rate shortage between the processor and the FPGA and reduce the footprint on the board.
This article describes how to access the Hard Processor System (HPS) and FPGA in Cyclone® V SoC FPGAs and Arria® V SoC FPGAs. In this article, unless otherwise noted, Cyclone® V SoC FPGA and Arria® V SoC FPGA are referred to as SoC FPGAs.
2. Interface between HPS and FPGA
The internal structure of the SoC FPGA is shown in the figure below. The green area at the top of the figure is the FPGA fabric, and the dashed line including the light blue area at the bottom is the HPS.
Figure 2-1. Internal Structure of an SoC FPGA
The SoC FPGA has four interfaces between the FPGA and the HPS.
The HPS side acts as the bus master and accesses the FPGA side through two interfaces: a high-bandwidth HPS-to-FPGA (H2F) interface with a maximum width of 128 bits and a 32-bit wide Lightweight HPS-to-FPGA (LWH2F) interface.
The H2F interface transfers relatively large amounts of data between the HPS and FPGA.
The LWH2F is suitable for relatively low-speed accesses such as control signals.
From the HPS, these interfaces are accessible as memory-mapped I/O on the address map described below.
An interface where the FPGA side acts as bus master and accesses the HPS side is the FPGA-to-HPS (F2H) interface with up to 128 bits.
The FPGA-to-SDRAM (F2S) interface is used to access the SDRAM controller on the HPS side directly from the FPGA side.
An overview of each interface is shown in the table below.
| Name | HPS to FPGA Bridge |
Lightweight HPS to FPGA Bridge |
FPGA to HPS Bridge | FPGA to HPS SDRAM Interface |
| Abbreviation | H2F | LWH2F | F2H | F2S |
| Function Overview | Interface where the HPS is the bus master and accesses the FPGA side | Interface where the HPS is the bus master and accesses the FPGA side | Interface where the FPGA is the bus master and accesses the HPS side | Interface where the FPGA becomes the bus master and directly accesses the SDRAM on the HPS side |
| Bus width | 32 / 64 / 128bit | 32 / 64 / 128bit | 32 / 64 / 128bit | 32 / 64 / 128 / 256 bit |
| Space size | 960MB | 2MB | 4GB | 4GB |
| I/F Type | AXI3™ | AXI3™ | AXI3™ | AXI3™ / Avalon®-MM |
| Maximum number of ports | 1 | 1 | 1 | AXI3™: 3 Avalon®-MM: 6 |
| Main usage | Data transfer to and from the FPGA side (when handling large size data requiring high bandwidth) | Read/write of the control status register (CSR) on the FPGA side (for low latency access without being affected by data traffic on the H2F) | Data transfer to and from the HPS side and CSR read/write | High-speed access to SDRAM on the HPS side (for accessing SDRAM without going through the main switch in the HPS) |
Since Platform Designer (formerly Qsys) automatically generates interconnect circuits for bus protocol interconversion, it is possible to connect components of the Avalon® interface to a bridge/interface with an I/F type of AXI3™. This makes it possible to reuse existing design assets.
3. Address Map
The FPGA as seen by the Arm processor can be accessed as a memory-mapped device. The address map is divided into the following three concepts depending on "where to access from".
- " MPU view " used when accessing from the Arm processor
- " L3 view (aka non-MPU view) " used when accessed from a master connected to the L3 interconnect (the concept of L3 (non-MPU) view is also applied to the master device on the FPGA side connected to F2H)
- " SDRAM view " used from the master connected to F2S
The concept of each view is shown in the figure below.
Figure 3-1. Concept of each view
Figure 3-2. Address Map for Each View
The above figure shows the address map for each of the three types of views.
- The MPU view and L3 (non-MPU) view are allocated fixed areas for H2F and LWH2F access.
- When accessing the FPGA from the HPS side via the H2F bridge, the address 0xC000_0000~ is accessed.
- When accessing the FPGA from the HPS side via the LWH2F bridge, the address 0xFF20_0000~ is accessed.
For information on how to access the FPGA from the Arm processor software, see " 5. Access from software".
Mapped to location 0x8000_0000~ or later in the L3 view (non-MPU view) is the Accelerator Coherency Port ("ACP"). Access via this port allows coherent access from and to the processor from a master connected to L3.
For access via ACP, please refer to the ACP description in the Hard Processor System Technical Reference Manual for the device family used.
4. Hardware Configuration
Hardware configuration is performed by Platform Designer. There are three configuration steps: "HPS Component Configuration," "Connecting the HPS to Other Components," and "Initializing the Interface.
4-1. HPS Component Settings (AXI Bridges / FPGA-to-HPS SDRAM Interface)
The HPS component settings are configured in the Platform Designer GUI.
Under the FPGA Interfaces tab, AXI Bridges (red box in the figure below) and FPGA-to-HPS SDRAM Interface (blue box in the figure below) are the relevant options.
Next, in the AXI Bridges settings, select the data bus width and whether or not to use it for the F2H, H2F, and LWH2F interfaces.
The FPGA-to-HPS SDRAM Interface setting allows the user to register multiple ports for the F2S interface, from 0 (unused) to a maximum of 6 ports depending on the conditions.
For details on the number of ports that can be registered for F2S, see section " 4-1-5. Number of F2S ports".
Figure 4-1. FPGA Interfaces Tab Settings
4-1-1. FPGA-to-HPS Interface (F2H)
The FPGA-to-HPS interface is used by the bus master in the FPGA to access peripherals and memory in the HPS.
This interface has a 4GB address space; bus masters that cannot support 32-bit addresses can be connected by address extension using the Address Span Extender (window bridge) in Platform Designer's IP catalog. The data bus width is 32 bits / 32 bits.
The data bus width can be selected from 32-bit, 64-bit, and 128-bit.
Figure 4-2. FPGA-to-HPS Interface (F2H)
4-1-2. HPS-to-FPGA Interface (H2F)
The HPS-to-FPGA interface is used by a bus master such as an Arm processor or DMA controller in the HPS to access peripherals in the FPGA.
A data bus width of up to 128 bits can be selected, making it suitable for large data transfers.
This interface has an address space of 960MB (0xC000_0000 to 0xFBFFFF_FFFFF); to access a space larger than 960MB, the Address Span Extender in the Platform Designer IP catalog (window Bridge) in Platform Designer's IP catalog.
The data bus width can be selected from 32-bit, 64-bit, and 128-bit.
Figure 4-3. HPS-to-FPGA Interface (H2F)
4-1-3. Lightweight HPS-to-FPGA Interface (LWH2F)
The lightweight HPS-to-FPGA interface is used by a bus master such as an Arm processor or DMA controller in the HPS to access peripherals in the FPGA.
Since the data bus width is fixed at 32 bits, it is suitable for controlling various registers such as LEDs and for accessing registers to check their status.
This interface has an address space of 2MB (0xFF20_0000 to 0xFF3F_FFFFFF).
If you want to access a space larger than 2MB, you can use the Address Span Extender (window bridge) in Platform Designer's IP catalog. The data bus width is 32 bits wide.
The data bus width is 32 bits only.
Figure 4-4. Lightweight HPS-to-FPGA Interface (LWH2F)
4-1-4. FPGA-to-HPS SDRAM Interface (F2S)
The FPGA-to-HPS SDRAM interface (F2S) is an interface that allows the bus master in the FPGA to access SDRAM in the HPS without having to go through the L3 interconnect in the HPS.
It can have up to 6 ports and 4GB of address space. Although 4GB of address space exists, do not access space that does not have a memory entity.
Four interface types can be selected.
-
- AXI-3
- Avalon-MM Bidirectional
- Avalon-MM Write-Only
- Avalon-MM Read-Only
The data bus width can be selected from 32bit / 64bit / 128bit / 256bit.
Figure 4-5. FPGA-to-HPS SDRAM Interface (F2S)
4-1-5. Number of F2S ports
We have already mentioned that the FPGA-to-HPS SDRAM interface (F2S) can have multiple ports. This section introduces the concept of the number of ports.
F2S is implemented with a command port (6 ports), a 64-bit read data port (4 ports), and a 64-bit write data port (4 ports).
As shown in the table below, the AXI bus uses two command ports and the Avalon®-MM bus uses one command port. Thus, up to three ports can be implemented for the AXI bus and up to six ports for the Avalon®-MM bus.
In terms of data bus width, up to 1 port can be implemented for a 256-bit bus, 2 ports for a 128-bit bus, and 4 ports for a 64-bit or 32-bit bus.
By combining the read only and write only ports of the Avalon®-MM, Figure 4-6 The F2 bus can be used for up to two ports.
Figure 4-6. F2S Port Type and Number of Ports
Figure 4-7. Number of Ports by Bus Protocol
4-1-6. SDRAM Controller Priority
The SDRAM controller implemented in the HPS implements arbitration logic to allow access from multiple ports. It is implemented in a weighted round-robin fashion, allowing weighting on a per-command-port basis as shown in the figure below.
For details, please refer to the SDRAM Controller Subsystem section of the Hard Processor System Technical Reference Manual for the device family used.
Figure 4-8. SDRAM Controller Block Diagram
Figure 4-9. Weighting by Command Port
4-2. Connecting to Other Components
To connect the HPS to other components, select an HPS interface (port) and connect it to one of the connectable interfaces (ports) on the other components in Platform Designer.
The HPS interface is an AXI interface, but Platform Designer automatically converts it so that either the Avalon®-MM interface or the AXI interface can be connected.
The addresses of the components in Platform Designer can also be set in the The addresses of the components in Platform Designer can also be set in the GUI. The software accesses the components based on the addresses set here.
Figure 4-10. Connecting HPS and other components in Platform Designer
4-3. Interface initialization
To use the interface between the HPS and FPGA, the registers in the HPS must be set. The user does not need to worry much about this because it is set by using a boot loader called Preloader if the following conditions are met.
- FPGA configuration has been completed before the Preloader is executed
- FPGA configuration is done during Preloader execution
4-3-1. Initialization of F2H, H2F, and LWH2F
The following two steps are required to use the HPS2FPGA (H2F) / LWHPS2FPGA (LWH2F) / FPGA2HPS (F2H) bridge.
(1) Release the bridge reset
Write 0x0 to the brgmodrst register (located at 0xFFD0_501C) (set each bit of bit0: H2F / bit1: LWH2F / bit2: F2H to 0: Reset release). See below for details.
(ii) L3 interconnect configuration
Write 0x18 to the remap register (at 0xFF80_0000) (set each bit of bit3: H2F / bit4: LWH2F to 1: Visible to L3 Master). See below for details.
The value to be written is design-dependent, so please check the details of each register before setting.
These initializations can be set by the bridge open command (bridge_enable_handoff / bridge enable) of U-Boot, which is introduced next.
4-3-2. Initialization of F2S
If SDRAM is not initialized by the preloader, the bridge cannot be accessed.
In addition, SDRAM must be in Idle state when changing F2S settings.
For this reason, it is recommended to execute the bridge open command (bridge_enable_handoff / bridge enable) implemented in U-Boot.
-
- In case of u-boot-socfpga_v2013.01.01 :.
$ run bridge_enable_handoff-
- In case of u-boot-socfpga_v2017.09 or later:
$ bridge enablePlease refer to the following page for the bridge open command between HPS and FPGA of U-Boot.
Reference information: U-Boot HPS-FPGA Bridge Open Command for SoC FPGAs
5. Access from software
The Arm® Cortex®-A9 MPCore processor and FPGA are bus-connected in the device, and peripherals in the FPGA can be viewed as memory-mapped I/O from the Arm processor.
Figure 5-1. Bus Connection within a Device
5-1. Addressing Concept
From the memory map, the base address of the HPS-to-FPGA (H2F) interface is 0xC000_0000 and that of the Light Weight HPS-to-FPGA (LWH2F) interface is 0xFF20_0000.
The address of the FPGA component as seen from the Arm processor can be calculated as follows
|
ARM from the FPGA The address of the FPGA component as seen from the ARM: Base address of the HPS-FPGA bridge + Offset address on Platform Designer ---------------------------------------------------------------- = Address of the FPGA component |
For example, to access the LED connected to 0x0002_0040 of LWH2F in Platform Designer, access the following address
|
Address for accessing PIO_LED from Arm processor: 0xFF20_0000 ( LWH2F base address) + 0x0002_0040 (offset address on Platform Designer) ---------------------------------------------------------------- |
Figure 5-2. Address when accessing PIO_LED from Arm processor
Figure 5-3. Code Example to Access PIO_LED from Arm Processor
5-2. System header file
In the previous example, the address of LED_PIO was defined in the source code and accessed. With this method, the source code may need to be changed every time hardware information is changed.
SoC FPGAs provide a mechanism to pass hardware information to software personnel. This mechanism is the System Header File Generator.
On the SoC EDS Command Shell, go to the directory containing the <qsys system>.sopcinfo file and run the command "sopc-create-header-files".
$ sopc-create-header-files <qsys subsystem>.sopcinfoPlease use the several header files that will be generated in terms of "which master to view from". An example of a header file is shown below.
Figure 5-4. Example of System Header File
6. Reference information
This article introduces the access method between HPS and FPGA in Cyclone® V SoC FPGA / Arria® V SoC FPGA. We hope this article will help you to use the SoC FPGA.
SoC FPGAs are available with various sample designs, so if you are new to using SoC FPGAs, it may be a good idea to try running a sample design on a development kit or the like to get a better understanding of the design.
Please refer to the following links for sample designs.
Reference information: Altera® SoC FPGA summary page (In Japanese)
Reference information: HPS-to-FPGA Bridges Design Example
Reference information: SoC FPGA Bare-metal Developer Center
Reference information: RocketBoards.org