Hello, my name is Totto.
This time, I have looked into the "half rate" (HDR), which is the type of clock rate for the local interface as described in the Spec Estimator. It is the red frame in the following screen.
What is HDR
HDR is a data transfer method that allows the data width of the local interface to be four times wider than the data width of the memory interface, thus reducing the frequency by half.
For Intel's FPGA memory interface, DDR3 is controlled by HDR , QDR ( Quarter Data Rate ).
DDR → SDR → HDR
DDR ( Double Data rate )
The memory controller in the FPGA takes data at the rising and falling edges of the clock.
The DATA in the figure below is 8 bits each.
DDR → SDR ( Single Data Rate )
In the FPGA, data is passed to the user circuitry in two steps. In the first step, double-rate data is converted to single-rate data.
Since data is taken only at the rising edge of the clock, DDR → SDR transfers data in parallel.
Since each data width is 8 bits, the total data width is 16 bits.
SDR → HDR (Half Data Rate)
As in SDR, data is taken at the rising edge of the clock, so data is transferred in parallel in SDR → HDR.
The difference, however, is that the operating frequency is halved. By halving the operating frequency, the data width is double that of SDR and four times that of DDR.
Since each data width is 8 bits, the total data width is 32 bits.
Even though HDR halves the operating frequency, the timing of data acquisition is the same as that of DDR by increasing the data width.
By converting DDR to HDR, the operating frequency is reduced and timing design becomes easier.
The clock frequency of QDR is a quarter of DDR and SDR, and the data width is 8 times.
Summary
HDR is a data transfer method that halves the frequency by making the data width of the local interface 4 times wider than the data width of the memory interface.
In the case of Intel's FPGA memory interface, DDR3 is controlled by HDR and QDR.
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