*This is an updated version of the former title "Techniques for using DS-5 - How to Use the Trace Function".
Arm® DS-5 for Intel® SoC FPGA Edition (DS-5) has been replaced by Arm® Development Studio for Intel® SoC FPGA Edition (Arm® DS), the standard software integrated development environment for Intel® SoC FPGAs. Arm® DS is the successor to DS-5 and is not significantly different in usability. Most of the articles in this series are applicable to both Arm® DS and DS-5, but the differences are clearly noted in this update.
***
This article provides additional information on how to use Arm® DS / DS-5, which is available as a software integrated development environment for Intel® SoC FPGAs.
In this article, we will show you how to use Arm® DS / DS-5 to obtain an instruction trace of software executing on an Intel® SoC FPGA device. By tracing the instruction execution history of the CPU with the trace function, you can trace back in time the detailed operation of the software up to the point where a failure or other event occurred.
The method described in this article uses an on-chip trace-only memory (32 KB in size) called Embedded Trace FIFO (ETF) to store the trace data. This method requires no additional equipment or hardware and requires only a target environment in which JTAG debugging can be performed. For more information on the trace feature, including optional settings not covered in this article, please refer to the Arm® DS / DS-5 manual.
Arm® Development Studio documentation page (Arm® Developer site)
DS-5 documentation page (Arm® Developer site)
Enabling Trace Functionality (DTSL Configuration)
The option to use the trace functionality of Arm® DS / DS-5 is configured through the Debug Trace Service Layer (DTSL) option available on the Connections tab of the Debug Configuration. Simply edit the DTSL option in the existing debug configuration settings to enable the trace functionality.
Figure 1. Debug Configuration - Connections Tab
DTSL Configuration Activation
Clicking the Edit...] button for the DTSL options button of the DTSL option launches the corresponding option setting window (DTSL Configuration). The initially selected [Cross Trigger] tab is for setting options related to debugging functions other than tracing and does not need to be edited. Edit the options on the other tabs to enable the trace function.
Figure 2. Activating DTSL Configuration
[Trace Capture] Tab
Figure 3. DTSL - Trace Capture Tab
[Cortex-A9] Tab
Figure 4. DTSL - Cortex-A9 Tab
[STM / ETR] Tabs
These tabs do not need to be edited.
The [STM] tab allows you to enable/disable System Trace Macrocell, if you want to record trace events other than CPU instruction traces. The [ETR] tab is only required when ETR is selected as the destination of the trace log, since the destination of the trace log is SDRAM in the case of ETR.
[ETF] Tab
Figure 5. DTSL - ETF Tab
When all tab options have been set, click the [OK] button to exit the DTSL configuration. Now it is time to start debugging.
Adding Trace Views
In Arm® DS, the view used for the trace function is not displayed on the standard screen layout, so you must add a trace view (a window that displays trace results) from the menu "Window → Show View → Trace" at the top of the Arm® DS screen. Similarly, a trace control view (a window for trace settings) can be added from "Window → Show View → Trace Control".
How to refer to the trace log
After debugging has started, the trace view is updated with the latest trace log every time the CPU stops running (break). Normally, the trace view is displayed as a sub-window as shown in the following image.
Figure 6. Debug screen 1 (normal screen layout)
The following image shows the tab of the trace view double-clicked and maximized.
Figure 7. Debug Screen 2 (Maximized Trace View)
In addition, clicking on a specific trace log allows contrast with the source code as shown below.
Figure 8. Debugging screen 3 (trace view maximized and source code displayed)
This is our introduction to how to use the trace function. It can be used with only simple settings, so please try using it when debugging.
Recommended articles/documents are here
How to use the debugger for SoC FPGAs (Arm® DS / DS-5)
Altera® SoC FPGA Summary Page
Development Flow of Altera® FPGAs