Altera® Cyclone® V SoC and Arria® V SoC families are manufactured on TSMC's 28nm Low Power (28LP) process technology, enabling low power consumption, a rich set of hardware IP, and low power serial transceivers.
Process Options in the 28nm Portfolio
The Cyclone® V SoC and Arria® V SoC families are differentiated by optimizations for performance, I/O resources, package size, power consumption, and cost requirements. The 28nm device family's common productivity-enhancing design platform enables rapid design development.
| Lowest static and absolute power consumption | Highest bandwidth |
| Lowest power transceivers | 28 Gbps transceivers with power consumption as low as 200mW |
| Adequate performance | Lowest power through design optimization |
| Maximum hard IP | |
| High-performance I/O standards |
Figure 1. Process Selection in 28nm Portfolio
Arria® V SoC FPGAs deliver 40% lower power consumption
Arria® V SX and ST SoCs offer the industry's lowest total power consumption for mid-range applications.
The 28nm Low-Power (LP) process reduces dynamic power consumption, enabling the following benefits
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Industry's lowest static power consumption Industry's lowest power consumption up to 10.3125Gbps transceivers Superior FPGA fabric with hard Intellectual Property (IP) |
Figure 2. 40% Lower Power in Arria® V SoC FPGAs
Arria® V FPGA Device Type Comparison
Table 1. Comparison of Arria® V FPGA Device Types
| Function | Arria V GZ FPGA | Arria V GT FPGA | Arria V GX FPGA | Arria V ST SoC | Arria V SX SoC |
| Number of ALMs (K) | 170 | 190 | 190 | 174 | 174 |
| Variable Precision Number of DSP Blocks | 1,139 | 1,156 | 1,156 | 1,068 | 1,068 |
| Number of M20K memory blocks | 1,700 | - | - | - | - |
| Number of M10K memory blocks | - | 2,414 | 2,414 | 2,282 | 2,282 |
| DDR3 Memory Interface Speed (MHz) | 800 | 667 | 667 | 667 | 667 |
| Hard Memory Controller | - | 4 | 4 | 4 | 4 |
| Transceiver Speed (Gbps) | 12.5 | 10.3125 | 6.5536 | 10.3125 | 6.5536 |
| PCI Express® (PCIe) Gen3/2/1 HIP | 1 | - | - | - | - |
| PCIe Gen2/1 HIP | - | 2 | 2 | 2 | 2 |
| Design & Security | ✔ | ✔ | ✔ | ✔ | ✔ |
| SEU Mitigation | ✔ | ✔ | ✔ | ✔ | ✔ |
Arria® V SoC FPGA Architecture
Figure 3. Arria® V SoC FPGA Architecture
Industry's Lowest Power Mid-Range FPGA
Arria® V GZ FPGAs have the lowest power consumption per bandwidth for mid-range applications, making them ideal for power-sensitive designs requiring transceivers up to 12.5 Gbps. The Arria® V GZ FPGAs consume less than 180 mW per channel at 10G and less than 200 mW at 12.5 Gbps. A -3L speed grade low static power product is also available.
Arria® V GX and GT FPGAs offer the lowest static power consumption on the 28nm Low-Power (LP) process and the lowest transceiver power consumption at transceiver speeds up to 10.3125 Gbps, as well as superior performance with hard IP designed to reduce dynamic power consumption. The Arria® V devices deliver an average of 40% power reduction over previous generation mid-range FPGAs.
SoC FPGAs - Customizable SoCs based on Arm® processors
Arria® V SoCs reduce system power consumption, system cost, and board space by integrating a hard processor system (HPS) consisting of a processor, peripherals, and memory controller with an FPGA fabric via a high-bandwidth interconnect backbone. The combination of the HPS and 28nm low-power FPGA fabric provides an application-class Arm® processor ecosystem and performance with the flexibility and rich DSP blocks of the Arria® V FPGA.
Cyclone® V FPGAs also reduce total power consumption by up to 40%.
Cyclone® V FPGAs are manufactured on TSMC's 28nm LP process, enabling them to deliver the performance required by cost-sensitive applications while reducing power consumption and cost.
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Benefits of 28nm LP include
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Figure 4. Cyclone® V FPGAs also reduce total power consumption by up to 40%.
The ability to be driven by only two supply regulator voltages and to be offered in wire-bond packages, including small packages, also contribute to cost savings.
The Cyclone® V FPGA family offers six different products
Table 2. The Cyclone® V FPGA Family Offers Six Product Types
| Features | Lowest cost and power consumption | 3.125G Transceivers | 6.144G transceiver |
| FPGA optimized for lowest system cost and power consumption, enabling a wide range of logic- and DSP-intensive applications | Lowest cost and power optimized FPGAs to enable 614Mbps to 3.125Gbps transceiver applications | Industry's lowest cost and lowest power FPGA to enable 6.144Gbps transceiver applications (*1) | |
| FPGAs | E Product | GX Product | GT Product |
| Arm® Cortex®-A9 MPCore™ processor system | SE Products | SX Products | ST Product |
(*1) Cyclone® V GT devices support the 6.144 Gbps CPRI protocol.
Cyclone® V System Integration Reduces System-Level Costs
Figure 5. Cyclone® V SoC FPGA System Integration
Ideal for Cost-Sensitive, High-Volume Applications
Cyclone® V FPGAs are ideal for high-volume applications such as protocol bridging, motor control drives, broadcast video converter/capture cards, and portable devices. Discover the benefits of Cyclone® V FPGAs in a variety of markets.
SoC - Customizable Arm® Processor-Based SoC
Cyclone® V integrates a hard processor system (HPS) consisting of a processor, peripherals, and memory controller with an FPGA fabric via a high-bandwidth interconnect backbone to reduce system power consumption, system cost, and The combination of the HPS and 28nm low-power FPGA fabric provides an application-class Arm® processor ecosystem and performance with the flexibility, low power consumption, and low cost of the Cyclone® V FPGA.
Reduce Overall System Costs through System Integration
Cyclone® V FPGAs have a number of built-in hard IP blocks that can reduce overall system cost and power consumption and shorten design development time while providing product differentiation. Key hard IP blocks include
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Low-power devices with a variety of low-power techniques
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Hard Processor System (HPS): 4,000 MIPS performance at low power
Independent power plane
Software-controlled power management
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Figure 6. Low Power Techniques
SoC and 28nm Portfolio
When performance, power, and cost requirements cannot be reconciled, there is no better solution than Altera® 28nm portfolio.
Offering a range of advantages, from broad feature sets to application-focused solutions, the 28nm portfolio takes programmable logic to a new level, enabling more complex and differentiated solutions to be developed in less time and with less effort.