My name is Taro. This time, I would like to write about frequency division/multiplication using PLL (Phase Locked Loop).
As introduced in the previous "About Buffer" blog, the main components of PLL are PFD / CP, LPF, and VCO.
A PLL functions as a frequency divider / multiplier when a divider is added to the reference signal (REF) / feedback signal (FB).
In this article, I will write about the principle of this function.
Please refer to the article on PLL in Intel® FPGA here.
Frequency Divider by PLL
The PLL frequency divider circuit has a frequency divider attached to REF as shown in the figure below.
For example, if the input (IN) is 100 MHz and the divider divides by 4, REF is 1/4 of IN, or 25 MHz.
The PFD/CP then adjusts the phase/frequency of FB to match the phase/frequency of REF.
The PFD compares the phase/frequency of REF and FB and continues to output UP and DOWN signals until the phase/frequency of REF and FB are equal.
This is how frequency division is performed by the PLL.
However, looking at this block diagram, some people may think that frequency division can be achieved with a frequency divider alone, without going to the trouble of using a PLL.
If the purpose of frequency dividing is only to "divide," it can certainly be achieved with a frequency divider alone.
However, a PLL is necessary to synchronize input and output.
In addition, frequency division by PLL uses a VCO to generate a clock signal for the input signal, so the accuracy of the signal depends on the VCO.
A PLL using a VCXO (voltage controlled crystal oscillator) can provide a signal with higher accuracy than the input signal.
In addition, the frequency divider may exist not only before REF but also after OUT.
By using a combination of the frequency divider before REF and the frequency divider after OUT, it is possible to output a more flexible frequency.
Multiplication by PLL
Multiplication" means to multiply the input frequency by n times. At first, I was a little scared because the kanji characters are difficult to read.
The PLL multiplication circuit has a frequency divider attached to FB as shown in the figure below.
For example, if the input (IN) is 25 MHz and the divider divides the frequency by 5, the output will be 125 MHz, 5 times the input frequency, to adjust the FB to 25 MHz.
In this way, the PLL multiplies the frequency.
Combined frequency divider/multiplier PLL
The combination of frequency divider/multiplier with a PLL can be used to create more flexible frequencies.
For example, if the REF divider divides by N and the FB divider divides by M, the output frequency will be M/N times the input frequency.
As you can see from the above figure, the degree of freedom of the divider's M and N values is directly related to the degree of freedom of the frequency produced.
IDT's products are divided into two types: those with built-in Integer PLL and those with built-in Franctional PLL, where the " Integer" and "Franctional" refer to the M and N resolutions in the above figure.
The FemtoClock® NG from IDT allows the user to choose between Integer and Franctional FB frequency dividers, depending on the signal input to the pin.
The FemtoClock® NG features a very low phase Jitter, and the use of Franctional FB allows the frequency resolution to be increased to tens of Hz, The frequency resolution is increased by using the Functional FB, allowing the frequency to be set in steps of several tens of Hz. The output phase Jitter is 0.5 ps rms.
On the other hand, the Integer FB has a lower resolution than the Franctional FB, but the output phase Jitter is 0.2 ps rms, which is a very accurate frequency output. The choice of Integer or Franctional depends on the user's specifications, but in either case, the output signal Jitter is small!
Clock generators and synthesizers use this PLL principle to produce the desired frequency.
In the next article, I will write about the application of PLL.
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