Introduction
Nios® V/g implements a cache. For non-cacheable access, unlike Nios® II, the target region must be configured as a Peripheral Region.
This article describes how to configure the Peripheral Region for non-cacheable access in Nios® V.
1. How to set up Peripheral Region
Peripheral Region is configured in Parameters of Nios® V/g in Platform Designer.
You can configure regions for non-cacheable access under 'Memory Configurations -> Peripheral Regions'. Two regions can be set.
In the example below, 256KB from 0x0004_0000 to 0x0007_FFFF is set as the non-cacheable area.
Figure 1. Peripheral Regions setting screen of Nios® V
2. Difference from Nios® II
In the case of Nios® II, non-cacheable access could be performed by using functions such as IORD, IOWR, alt_uncached_malloc, alt_remap_uncached, etc. In Nios® V, however, it is necessary to set the Peripheral Region. Nios® V requires the Peripheral Region to be set.
In the case of Nios® II, as shown in the red box in the figure below, the default setting is to bypass the cache (non-cache access) by setting bit[31] of the address to 1.
When the option 'Use most-significant address bit in processor to bypass data cache' is enabled, you can bypass the cache either by using IORD/IOWR instructions or by accessing the base address with an offset of 0x8000_0000, without configuring the Peripheral Region.
If this is unchecked, Peripheral Region must be set. In this case, the same settings as in Nios® V are required.
Figure 2. Nios® II Cache Settings Screen
For more information on the differences in cache bypassing between Nios® II and Nios® V, please refer to the following document
Reference: AN 978: Nios® V Processor Migration Guidelines
Conclusion
In this article, we have shown how to perform non-cache access in Nios® V.
We have prepared a Nios® V summary page (In Japanese), so if you have any questions about Nios® V, please refer to this page as well.