About Traffic Generator 2.0, a user-configurable test pattern

Description.

The Altera^® Agilex™ FPGA & SoC family and the Altera^® Stratix^® 10 FPGA family allow user-configurable Traffic Generator The Traffic Generator 2.0 can be implemented in the Example Design of the External Memory Interface (EMIF) IP core.

The Traffic Generator 2.0 configuration and the patterns it executes are described in this document.

Links to related articles

Please refer to the following video for the procedure to execute Traffic Generator 2.0.

• Altera®Agilex™ FPGA & SoC External Memory Interface Traffic Generator 2.0

Please refer to the video below for instructions on how to run the EMIF Debug Toolkit, a function to check the calibration results.

• Altera® Agilex™ FPGA & SoC External Memory Interface Debug Toolkit

Attachment

External Memory Interface Example Design Traffic Generator 2.0