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Nios® V Boot Option ~ TCM Boot ~

Nios® V Boot Option ~ TCM Boot ~

  • Updated

Introduction

This article describes the IP and BSP Editor settings required to boot the Nios® V processor from Tightly Coupled Memory (hereafter referred to as TCM) and how to generate the TCM initial value file.

The content of this article is intended for those who are familiar with the procedure for developing configurations using Nios® V. If you are new to Nios® V, please refer to the content below.

____.png Reference materials: Ashling* RiscFree* IDE for Nios® V Project Development

 

1. What is TCM?

TCM is a memory directly attached to the processor. It is often used in applications that require real-time performance because it can be used in a cache-like fashion with no miss-hits and fast access. 
TCM has the following features

  • Low latency and high-speed access
  • No access contention

Access to memory through the FPGA interconnect usually takes at least two clocks, whereas TCM requires at least one clock. 
TCM is an option implemented in the Nios® V/g processors and is available in the following Quartus® Prime The TCM is an option implemented in the Nios® V/g processors and is available from the following Quartus® Prime versions

  • Quartus® Prime Pro Edition Version 23.3
  • Quartus® Prime Standard Edition Version 23.1 
     

2. Hardware Setup and Design Configuration

This chapter describes the minimum IP and settings required to boot Nios® V with TCM.

2-1 Platform Designer Configuration and IP Settings

The following figure shows an example of Platform Designer system design.

Figure 1: Platform Designer System Overview 
 

The following IPs are required for TCM Boot of Nios® V at a minimum.

  •  
    • Clock Bridge FPGA IP (Clock in the above figure)
    • Reset Bridge FPGA IP (Reset shown above)
    • Nios® V/g General Purpose Processor FPGA IP (NiosV shown above)

IPs other than the above (PIO, etc.) should be used according to the user's system specifications.

2-1-1. Nios® V/g Processor Settings

Configure the Nios® V/g processor settings in the Parameter Editor of Platform Designer. 
First, configure the Instruction TCM1 tab and Data TCM1 tab of Tightly Coupled Memories from the Memory Configurations block. 
Set the size, base address, and initial value file for each TCM with reference to the figure below.

Figure 2: Instruction TCM Tab Settings 
 

Figure 3: Data TCM Tab Settings 
 

After setting each TCM, check the Nios® V processor in the System View of Platform Designer, and you will see that the ports in the red frame below have increased. These ports are the interface to TCM, so connect the instruction_manager and data_manager of Nios® V as shown in the figure below.

Figure 4: Connecting TCM interfaces 
 

After connecting, instruction_tcs1 is mapped and a base address is assigned. Set this base address to the same address as the instruction TCM1 base address set in the Parameter Editor.

Figure 5: Base address of Instruction TCM 
 

After completing the above, check the Parameter Editor again and set Reset Agent to Instruction TCM1 from the Traps, Exceptions, and interrupts block (niosvitcm1 is used in this article). Figure 6.)

Figure 6: Reset Vector Settings 
 

__.png Note : Please note that in Quartus® Prime Pro Edition Version 24.3 or earlier, the above settings are in the Vectors block.

Please run "Generate HDL" in Platform Designer to generate various files.

2-2. Quartus® Prime Settings

In Quartus® Prime, configure the FPGA configuration scheme. 
Open Assignments tab → Device → Device and Pin Options → Configuration.

  •  
    • Configuration scheme: Set the FPGA's configuration scheme
    • Active serial clock source: Set the clock frequency when configuring the FPGA

The figure below is an example, so please make settings according to the specifications of the board you are using.

Figure 7: Configuration scheme settings

 

3. Software configuration

In this chapter, we will introduce the BSP settings required to boot Nios® V from TCM using the BSP Editor. If you do not know how to create the file, please refer to the following link.

____.png References: Nios® V Project Development Procedure Using Ashling* RiscFree* IDE -> 4. Development of Nios® V with RiscFree* IDE

The following is a description of Linker Script settings and hal.linker settings.

To set the Linker Script, select the BSP Linker Script tab from the BSP Editor , set Instruction TCM1 (niosvitcm1) in .text and .exceptions, and set Data TCM 1 (niosvdtcm1) in the remaining Linker Section Name.

Figure 8: BSP Linker Script Tab Settings 
 

To set hal.linker, go to Settings -> Advanced -> hal in the Main tab and enable only allow_code_at_reset for the hal.linker option.

Figure 9: Setting of hal.linker 

 

4. Generation of programming file (HEX file)

After the software compilation is completed and the ELF file is generated, generate the HEX file to be registered as the initial value of TCM.

Please refer to the following article for the procedure up to the generation of the ELF file.

____.png Reference material: Nios® V Project Development Procedure Using Ashling* RiscFree* IDE -> 4-4. Starting up RiscFree* IDE

To boot the Nios® V processor from TCM, use the Nios® V command shell to convert the application ELF file to a HEX file. Create the itcm.hex and dtcm.hex files for the user application with the following commands:

  • Generate itcm.hex command (initial value file for Instrcution TCM)
elf2hex software/app/build/<user_application>.elf -o itcm.hex -b <base address of ITCM> -w 32 -e <end address of ITCM> -r 4
  • Execution example
elf2hex software/app/build/app.elf -o itcm.hex -b 0x00040000 -w 32 -e 0x0007ffff -r 4
  • Generate dtcm.hex command (initial value file for Data TCM)
elf2hex software/app/build/<user_application>.elf -o dtcm.hex -b <base address of DTCM> -w 32 -e <end address of DTCM> -r 4
  • Execution example
elf2hex software/app/build/app.elf -o dtcm.hex -b 0x00080000 -w 32 -e 0x000bffff -r 4

The file generated by the above command is the initial value file of TCM set in section 2-1-1. Nios® V/g Processor Settings.

After the above settings are made and the FPGA is compiled, a configuration file with the TCM Boot settings completed will be generated. 

 

Conclusion

In this article, we have shown how to boot Nios® V from TCM using TCM.

For more information on the Nios® V processor, please refer to the manufacturer's page below.

__.png Reference: Nios® V Processor Developer Center

We have also compiled information on Nios® V into the "Nios® V Summary" page. The Nios® V Summary Page which contains a summary of information on Nios® V. Please refer to this page as well, as it contains useful information other than this article.

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