1. Introduction
Stratix® 10 FPGAs and Agilex™ 7 FPGAs have a built-in hardware module called the Secure Device Manager (SDM) that performs configuration and booting. Since the configuration/booting is done by SDM, the boot method is different compared to previous devices, The boot method is different compared to previous devices.
In this article, Stratix® 10 FPGA/Agilex™ 7 FPGA This article describes the different boot methods and their settings for the Stratix® 10 FPGA/Agilex™ 7 FPGA, This article describes the types of boot methods and their settings.
2. Types of Boot Methods
Stratix® 10 FPGA/Agilex™ 7 FPGA offers the following two boot methods.
- HPS Boot First mode
- FPGA Configuration First mode
2-1. HPS Boot First mode
HPS Boot First mode is a mode in which the HPS is booted prior to the FPGA configuration.
The following figure shows the sequence of HPS Boot First mode, The figure below shows the sequence of HPS Boot First mode, and you can see that HPS boot is performed before FPGA configuration.
Figure 1. HPS Boot First Flow
* Excerpt from Stratix® 10 SoC FPGA Boot User Guide
2-2. FPGA Configuration First mode
FPGA Configuration First mode is a mode in which FPGA configuration is performed before HPS boot.
The following figure shows the sequence of FPGA Configuration First mode, The figure below shows the sequence of FPGA Configuration First mode, and you can see that the FPGA configuration is done before the HPS boot.
Figure 2 FPGA Configuration First Boot Flow
* Excerpt from Stratix® 10 SoC FPGA Boot User Guide
2-3. How to Decide on the Boot Method
We have explained that there are two boot methods, HPS Boot First mode and FPGA Configuration First mode.
Which boot method should I actually choose?
The boot method should be decided according to your "product specification".
You should consider which is more convenient for your product to boot first, HPS or FPGA.
However, if you are using PCI Express, you must use the FPGA Configuration First mode.
This is because PCI Express has a specification that the PCI Express part must be configured within 100ms after the device is powered on.
3. boot method configuration
This chapter describes the boot method settings and the Golden Hardware Reference Design (GHRD) settings.
3-1. Setting in Device and Pin Option
The boot method setting is within Device and Pin Options of Quartus® Prime.
The Device and Pin Options can be started with the following flow.
From the Quartus menu bar, select [Assignments] ⇒ [Device...] ⇒ [Device and Pin Options...].
■ Set the boot method in the "HPS/FPGA configuration order:" field.
- Select " After INIT_DONE " to set the FPGA Configuration First mode.
- Select " HPS First " to set the HPS Boot First mode.
The figure below shows an example of boot method setting.
Figure 3. Boot method setting items
3-2. settings at the time of GHRD generation
GHRD is obtained from Github, and the design is generated by executing the script.
Reference: Please refer to the following contents for information on how to obtain and generate GHRDs.
How to obtain and generate SoC FPGA Hardware Reference Design (GHRD)
Before generating a design, set the BOOTS_FIRST item in the Makefile to generate a design to which the settings described in section 3-1 "Device and Pin Option Settings" have already been applied (see Figure 4).
Figure 4. Example of boot method setting in GHRD Makefile
4. file to be stored in Flash
This chapter introduces the files to be stored in Flash for each boot method.
There are two Flash configurations, Single Flash and Dual Flash, butthe major configuration, Dual Flash, is used in this section. Reference: Please refer to the following document for Single Flash configuration.
Stratix® 10 SoC FPGA Boot User Guide
Note that the file extensions may change depending on the U-boot version and Linux environment.
Reference: The files in this chapter are based on the following Rocketboards.org article (as of 2022/03/11).
Building Bootloader for Stratix 10 and Agilex
4-1. Flash Internal Configuration in HPS Boot First mode
The required files for HPS Boot First mode are shown below. Please refer to Figure 5.
① Bitstream : .jic file
* Please refer to the supplementary explanation in " 4-3. Supplementation".
* FSBL stands for First Stage Boot Loader
② HPS SSBL: u-boot.itb
SSBL stands for Second Stage Boot Loader
③ Kernel image & DTB : <Linux kernel/dtb
④ FPGA Core & I/O Configuration : rbf file
⑤ OS File System : <rootFs related>
Figure 5. Dual Flash configuration at HPS Boot First
* Excerpt from Stratix® 10 SoC FPGA Boot User Guide
In HPS Boot First mode, the FPGA configuration is done from the HPS side, so the configuration data is included in the Flash on the HPS side.
Point: If the FPGA configuration is done after the OS (Linux) is booted, the configuration in the OS File System (⑤) may be used instead of in the FAT partition (④).
4-2. Flash Internal Configuration in FPGA Configuration First mode
The required files for FPGA Configuration First mode are shown below. Refer to Figure 6 for details.
① Bitstream : .jic file
* See the supplementary explanation in " 4-3. Supplementation".
② HPS SSBL : u-boot.itb
③ Kernel image & DTB : <Linux kernel/dtb>
④ OS File System : <rootFs related>
Figure 6. Dual Flash configuration during FPGA Configuration First
* Excerpt from Stratix® 10 SoC FPGA Boot User Guide
In FPGA Configuration First mode, the FPGA configuration is done on the FPGA side, so the configuration data is included in the Flash on the FPGA side.
4-3. Supplementation
The following two points are additional information about the Bitstream in the Flash on the FPGA side.
1. The location of the FPGA core differs depending on the boot method set.
The location of the FPGA core for each boot method is as shown in the table below.
Table 1. Location of FPGA core by boot method
| Boot method | FPGA core location |
| FPGA Configuration First |
FPGA side Flash No special processing is required as it is automatically included in the .sof file generated by compilation. |
| HPS Boot First |
HPS side Flash In case of HPS Boot First, FPGA is configured from HPS side. When configuring FPGA from U-boot, the .rfb file is stored in Flash on the HPS side. |
2. FSBL must be embedded in Bitstream
Since the HPS is booted by the SDM on the FPGA side, the FSBL must be included in the Flash on the FPGA side.
Refer to the figure below for the command to include the FSBL in the .sof file.
Figure 7. Command for creating .sof file including FSBL
* Excerpt from Stratix® 10 SoC FPGA Boot User Guide
5. Boot log
The HPS boot log differs depending on the boot method. This section describes the differences in the boot log.
5-1. Boot log in HPS Boot First mode
In HPS Boot First mode, the FPGA is configured after FSBL, so the configuration log is displayed.
The following log is for the case where the FPGA is configured in SSBL, so the configuration log is output in the SSBL phase.
U-Boot SPL 2021.07 (Nov 15 2021 - 16:50:42 +0000)
Reset state: Cold
MPU 1200000 kHz
L4 Main 400000 kHz
L4 sys free 100000 kHz
L4 MP 200000 kHz
L4 SP 100000 kHz
SDMMC 50000 kHz
DDR: 8192 MiB
SDRAM-ECC: Initialized success with 1727 ms
QSPI: Reference clock at 400000 kHz
WDT: Started with servicing (10s timeout )
denali-nand-dt nand@ffb90000: timeout while waiting for irq 0x2000
denali-nand-dt nand@ffb90000: reset not completed.
Trying to boot from MMC1
## Checking hash(es) for config board-0 ... OK
## Checking hash(es) for Image atf ... crc32+ OK
## Checking hash(es) for Image uboot ... crc32+ OK
## Checking hash(es) for Image fdt-0 ... crc32+ OK
NOTICE: BL31: v2.5.1(release):QPDS21.4_REL_GSRD_PR
NOTICE: BL31: Built : 06:53:56, Dec 29 2021
U-Boot 2021.07 (Dec 02 2021 - 03:12:39 +0000) socfpga_agilex
CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)
Model: SoCFPGA Agilex SoCDK
DRAM: 8 GiB
WDT: Started with servicing (10s timeout)
NAND: denali-nand-dt nand@ffb90000: timeout while waiting for irq 0x2000
denali-nand-dt nand@ffb90000: reset not completed.
Failed to (error -5)
0 MiB
MMC: dwmmc0@ff808000: 0
Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1... Loading Environment from SPIFlash... SF: Detected mt25qu02g with page size 256 Bytes, erase size 4 KiB, total 256 MiB
OK
In: serial0@ffc02000
Out: serial0@ffc02000
Err: serial0@ffc02000
Net
Warning: ethernet@ff800000 (eth0) using random MAC address - 96:c1:d7:95:49:fb
eth0: ethernet@ff800000
Hit any key to stop autoboot: 5 4 3 2 1 0
switch to partitions #0, OK
mmc0 is current device
Scanning mmc 0:1. .
Found U-Boot script /boot.scr.uimg
2195 bytes read in 3 ms (713.9 KiB/s)
## Executing script at 05ff0000
crc32+ Trying to boot Linux from device mmc0
Found kernel in mmc0
13643679 bytes read in 622 ms (20.9 MiB/s)
## Loading kernel from FIT Image at 02000000 ...
Using 'board-0' configuration
Verifying Hash Integrity ... OK
Trying 'kernel' kernel subimage
Description: Linux Kernel
Type: Kernel Image
Compression: lzma compressed
Data Start: 0x020000dc
Data Size:. 8226617 Bytes = 7.8 MiB
Architecture: AArch64
OS: Linux
Load Address: 0x06000000
Entry Point: 0x06000000
Hash algo: crc32
Hash value: c6de3509
Verifying Hash Integrity ... crc32+ OK
## Loading fdt from FIT Image at 02000000 ...
Using 'board-0' configuration
Verifying Hash Integrity ... OK
Trying 'fdt-0' fdt subimage
Description: socfpga_socdk
Type: Flat Device Tree
Compression: uncompressed
Data Start: 0x027d88f4
Data Size: 19372 Bytes = 18.9 KiB
Architecture: AArch64
Hash algo: crc32
Hash value: dfa04e7e
Verifying Hash Integrity ... crc32+ OK
Booting using the fdt blob at 0x27d88f4
## Loading fpga from FIT Image at 02000000 ...
Trying 'fpga-0' fpga subimage
Description: FPGA bitstream for GHRD
Type: FPGA Image
Compression: uncompressed
Data Start: 0x027e6740
Data Size: 1839104 Bytes = 1.8 MiB
Load Address: 0x0a000000
Hash algo: crc32
Hash value: 6ec82c4a
Verifying Hash Integrity ... crc32+ OK
Loading fpga from 0x027e6740 to 0x0a000000
..FPGA reconfiguration OK! ##Comment: FPGA configuration completed at SSBL
Enable FPGA bridges
Programming Full bitstream... OK
Uncompressing Kernel Image
Loading Device Tree to 000000007f9ed000, end 000000007f9f4bab ... OK
SF: Detected mt25qu02g with page size 256 Bytes, erase size 4 KiB, total 256 MiB
Enabling QSPI at Linux DTB. .
RSU: Firmware or flash content not supporting RSU
RSU: Firmware or flash content not supporting RSU
RSU: Firmware or flash content not supporting RSU
RSU Firmware or flash content not supporting RSU
5-2. Boot log in FPGA Configuration First mode
In FPGA Configuration First mode, the configuration is already done before FSBL is started, so the configuration log is not output.
U-Boot SPL 2021.07-16361-g24e26ba4a0 (Mar 29 2022 - 09:03:53 +0900)
Reset state: Cold
MPU 1200000 kHz
L3 main 400000 kHz
Main VCO 2400000 kHz
Per VCO 2000000 kHz 115200 8N1 NORinicom 2.6.2 | VT102 \u5207\u65ad EOSC1 25000 kHz
HPS MMC 50000 kHz
UART 100000 kHz
DDR: 4096 MiB
SDRAM-ECC: Initialized success with 1001 ms
QSPI: Reference clock at 400000 kHz
WDT: Started with servicing (10s timeout)
denali-nand-dt nand@ffb90000: timeout while waiting for irq 0 x2000
denali-nand-dt nand@ffb90000: reset not completed.
Trying to boot from MMC1
## Checking hash(es) for config board-0 ... OK
## Checking hash(es) for Image atf ... crc32+ OK
## Checking hash(es) for Image uboot ... crc32+ OK
## Checking hash(es) for Image fdt-0 ... crc32+ OK
NOTICE: BL31: v2.5.1(release):rel_socfpga_v2.5.1_22.03.01_pr
NOTICE: BL31: Built : 08:17:23, Mar 29 2022
U-Boot 2021.07-16361-g24e26ba 4a0 (Mar 29 2022 - 09:03:53 +0900)socfpga_stratix10
CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)
Model: SoCFPGA Stratix 10 SoCDK
DRAM: 4 GiB
WDT: Started with servicing (10s timeout)
NAND: denali-nand-dt nand@ffb90000: timeout while waiting for irq 0x2000
denali-nand-dt nand@ffb90000
Failed to initialize Denali NAND controller.(error -5)
0 MiB
MMC: dwmmc0@ff808000: 0
Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1... LoadiB
*** Warning - bad CRC, using default environment
Loading Environment from UBI... denali-nand-dt nand@ffb90000: timeout while wai0
denali-nand-dt nand@ffb90000: reset not completed.
Could not find a valid device for ffb90000.nand .0
Partition root not found!
** Cannot find mtd partition "root"
In: serial0@ffc02000
Out: serial0@ffc02000
Err: serial0@ffc02000
Net:
Warning: ethernet@ff800000 (eth0) using random MAC address - 22:22:46:53:47:0b
eth0: ethernet@ff800000
6. Reference materials
The following are some reference materials.
Reference: User Guide
Stratix® 10 SoC FPGA Boot User Guide
Reference: Macnica Technical Content
How to Obtain & Generate SoC FPGA Hardware Reference Designs (GHRD)
7. Conclusion
This article described the boot method for Stratix® 10 FPGAs and Agilex™ 7 FPGAs. I hope this article will give you an idea of HPS Boot First and FPGA Configuration First. I hope this article will give you an idea of what HPS Boot First and FPGA Configuration First are all about.
The configuration is very easy, We hope you will try both boot methods.