Skip to main content

Debugging Nios V with VS Code - Ashling Visual Studio Code Extension for Altera FPGAs -

Debugging Nios V with VS Code - Ashling Visual Studio Code Extension for Altera FPGAs -

  • Updated

This article describes the procedure for debugging Nios V using the Visual Studio Code (VS Code) extension provided by Ashling.

Normally, debugging for Nios V is done using the RiscFree IDE, an eclipse-based integrated development environment provided by Ashling, but we understand that some users may prefer to debug with VS Code, which they are familiar with. To meet this need, we have developed an extension for VS Code, which requires setup, but can be used according to the user's preference.

This article is based on the chapter "3. Ashling Visual Studio Code Extension for Altera FPGAs" in the following user manual.

Note: Some screen captures in this article are shown together due to differences in the UI between the Japanese and English versions. Please check the screen capture according to your environment.

 

Verification Environment

The following tool versions are used for verification. This article is written for the Standard Edition, but the basic operations are the same.

 

Installation

Installing Quartus Prime

Quartus Prime and Ashling RiscFree IDE must be installed beforehand. This procedure is omitted from this article.

 

Installing Ashling Visual Studio Code Extension for Altera FPGAs

Open VS Code.

 

Select Install from VSIX from the Extensions menu on the left.

 

Select the following folder under the Ashling RiscFree IDE installation directory Specify the .vsix file stored in the folder and click the Install button.

  • C:\intelFPGA_standard\24.1std\riscfree\vscode

 

After the installation is complete, the Ashling menu will be added to the left menu bar.

 

Follow the instructions in the manual to install the following additional extensions

  • C/C++
  • CMake
  • CMake Tools
  • debug-tracker-vscode
  • Embedded Tools
  • Peripheral Viewer
  • Memory View

 

Note: Ashling VS Code Extension is also registered as a standard extension for VS Code and newer versions are available for installation. (As of 2025/05/15)

We have confirmed that the new version will work properly, but we do not guarantee that it will work.

 

Initial configuration of the tool

Next, perform the initial settings of the installed VS Code extension.

Select "Open Plugin Settings" from the Ashling menu.

 

Specify the directory of the RiscFree IDE that has been installed separately in the Installation Path. This is especially important if you have multiple versions of the RiscFree IDE installed.

In our example, we specify the following path

  • C:\intelFPGA_standard\24.1std\riscfree

 

Check tool installation status and dependencies

Then select "Verify and Confirure Dependencies" and check if the tools are installed correctly.

 

If it is installed without problems, the following log will be output.

 [16:01:22] Starting Quartus installation search... 
[16:01:24] Checking environment variables: 
[16:01:24] QUARTUS_ROOTDIR: C:\intelFPGA_standard\24.1std\quartus 
[16:01:24] QUARTUS_ROOT: not set 
[16:01:24] ALTERA_ROOT: not set 
[16:01:24] ✅ Found Quartus installation(s) at: C:\intelFPGA_standard\24.1std\quartus 
[16:01:24] Searching for RiscFree installation. for RiscFree installation... 
[16:01:26] Checking for RiscFree at: C:\intelFPGA_standard\24.1std\riscfree 
[16:01:26] ✅ Valid RiscFree installation found at: C:\intelFPGA_ standard\24.1std\riscfree 
[16:01:26] Verifying RiscFree toolchain... 
[16:01:28] Setting up VS Code configuration... 
[16:01:29] ✅ Setup completed successfully! 
[16:01:29] 
Checking toolchain components... 
[16:01:29] Checking Ashling SDK Installation 
================================ 
[16:01:29] Verifying Build Tools 
------ ------------------------- 
 Checking CMake........ ✅ 
 Location: C:\intelFPGA_standard\24.1std\riscfree\build_tools\cmake\bin\cmake.exe 
 Getting version........ 3.31.1 
 Checking Make........ ✅ 
 Location: C:\intelFPGA_standard\24.1std\riscfree\build_tools\bin\make.exe 
 Checking Ashling CLI........ ✅ 
 Location: C:\intelFPGA_standard\24.1std\riscfree\cli\ashling-cli.exe 
[16:01:31] Verifying Debug Tools 
------------------------------- 
 Checking ARM GDB Server........ ✅ 
 Location: C:\intelFPGA_standard\24.1std\riscfree\debugger\gdbserver-arm\ash-arm-gdb-server.exe 
 Checking RISC-V GDB Server........ ✅ 
 Location: C:\intelFPGA_standard\24.1std\riscfree\debugger\gdbserver-riscv\ash-riscv-gdb-server.exe 
 Checking QEMU RISC-V........ ✅ 
 Location: C:\intelFPGA_standard\24.1std\riscfree\qemu\qemu-system-riscv32.exe 
 Getting version........ 9.0.2 
[16:01:35] Verifying RISC-V Toolchain 
------------------------------------ 
 Checking RISC-V GCC (32-bit)........ ✅ 
 Location: C:\intelFPGA_standard\24.1std\riscfree\toolchain\riscv32-unknown-elf\bin\riscv32-unknown-elf-gcc.exe 
 Getting version ........ 13.2.0 
 Checking RISC-V G++ (32-bit)........ ✅ 
 Location: C:\intelFPGA_standard\24.1std\riscfree\toolchain\riscv32-unknown-elf\bin\riscv32-unknown-elf-g++.exe 
 Checking RISC-V GDB (32 -bit)........ ✅ 
 Location: C:\intelFPGA_standard\24.1std\riscfree\toolchain\riscv32-unknown-elf\bin\riscv32-unknown-elf-gdb.exe 
 Getting version Version unknown ........ Version unknown 
[16:01:38] Verifying ARM Toolchain 
--------------------------------- 
 Checking ARM GDB (AArch64 ELF)........ ✅ 
 Location: C:\intelFPGA_standard\24.1std\riscfree\toolchain\Arm\aarch64-none-elf\bin\aarch64-none-elf-gdb.exe 
 Getting version........ Version unknown 
[16:01:41] Summary 
======= 
Components Found: 10/10 
✅ All components verified successfully

 

Setup is now complete.

 

Project Generation and Debugging

Preparing the Hardware Design

In order to perform the following steps from this point forward, you will need to prepare a hardware design that includes Nios V. In this article, we have used the DE10-Nano as the target, but please modify it according to the board you are using.

Note: The Hello World sample for Nios V requires about 100KB of memory, as described in the ReadMe, so please keep this in mind when preparing your design.

 TITLE: 
Readme - Hello World Software Example 

DESCRIPTION: 
Simple program that prints "Hello World" in a loop. 

The memory footprint of this hosted application is intended to be small (~100 kbytes) by default 
using a standard reference deisgn. 

PERIPHERALS USED: 
This example exercises the following peripherals: 
- STDOUT device (UART or JTAG UART)

 

The Platform Designer configuration of the design used is as follows

Nios V/m is selected as the Nios V core, and 128KB of on-chip memory is provided as work memory. In addition, JTAG_UART is implemented as a printf output destination, and PIO is not required to execute Hello_World.

 

Generating BSP

Open the prepared hardware design directory in VS Code.

 

Select "Nios V BSP Generator" from the Ashling menu. Click "Yes" on the pop-up window to start the GUI.

 

The BSP Editor starts up.

 

Select "New BSP..." from the File menu. from the File menu.

 

Specify the .sopcinfo file included in the hardware design. In this example, niosv_system.sopcinfo is specified.

 

Click "Generate" to generate BSP with default settings. When completed, click "Exit" to close the screen.

 

When generation is complete, the BSP will be generated for the default path shown in the window specifying the .sopcinfo file above. In this example, the output will be in the following path.

  • C:\vscode_test\software\hal_bsp

 

Generating the application

Next, the application side is generated.

Select "Nios V App Generator" from the Ashling menu.

 

A dedicated GUI will be launched as a tab.

 

Specify the following path where you generated the BSP for the BSP path.

  • C:\vscode_test\software\hal_bsp

Specify hello_world as the sample selection. Leave "Add applocation to the workspace" checked, as it will affect the directory where the artifacts generated by CMake will be created.

 

 

When generation is complete, the following popup will be displayed.

In addition, "app" will be added to the Ashling menu. This is achieved by leaving the "Add applocation to the workspace" checkbox checked in the previous step.

 

Building the application

Select "Build" on the app side.

 

The following candidates will be displayed in the menu at the top, and Ashling RISC-V GNU GCC toolchain is specified.

 

If the build is successful, you will see that the build directory is created under software/app, and app.elf is created in the directory.

 

 

Debugging

From this point on, you will need an actual device. Please write the hardware design to the board in advance.

 

Debug Configuration

From the Ashling menu, select the "+" button next to Debug Configuration.

 

Select "Nios V Hardware Debugging" and you will be prompted to enter a name for the configuration.

Enter a name of your choice and press "Enter. In this example, the name "niosv_test" is used.

 

The debug configuration setting screen will open, so configure it according to the target board. Click "Auto-detect Scan Chain" to select the target device from the list of devices in the JTAG chain.

Note: If the device has an HPS, the JTAG on the HPS side is displayed in some cases, so be sure to select the JTAG device on the FPGA side.

 

Click the "Debug" button in the upper right corner to start debugging.

When the connection is complete, the program will break at the beginning of the main statement and stop.

At this point, you should be able to operate the device intuitively while looking at the screen. Please refer to the manual introduced at the beginning of this document for details on how to operate the debug window.

 

Summary

The VS Code extensions make it easy to debug Nios V with a familiar VS Code environment. It is also possible to generate BSPs and applications using a GUI, which is usually a command-line operation.

 

Reference Information

 

 

Related articles