Getting Started with Transceivers: Agilex™ 5 / Agilex™ 3 Edition, Basics Part 1 - Design Creation – Macnica Altera FPGA Insights

Introduction

This article is the Basics Part 1 of the "Getting Started with Transceivers Agilex™ 5 / Agilex™ 3 Edition" series, explaining how to create a design that includes a transceiver. The design creation uses the Platform Designer in Quartus® Prime Pro Edition. For more details on Platform Designer, please refer to the following:
Quartus® Prime Pro Edition User Guide: Platform Designer

Additionally, a sample file of the design created in this article is attached at the end.

1. Overview of the Design to be Created

1-1. Overview of the Design

The design to be created is the "xcvr_sample.qsys" part shown in the figure below, created using Platform Designer.

1-2. Block Structure of the Design

The block structure of the design to be created is as follows. This is the minimum necessary configuration.

Transceiver (GTS PMA/FEC Direct PHY IP)
Reset Sequencer IP
Reset Release IP

Depending on the PHY settings, a block called System PLL may be required; however, this design does not use it. A design using System PLL will be introduced in a future article.

The content of each block is as follows.

Block Name	Description	User Guide
Transceiver (GTS PMA/FEC Direct PHY)	PHY block. Performs parallel-to-serial and serial-to-parallel conversion.	GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs
Reset Sequencer	Handles transceiver reset processing. One is implemented on each side.	GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs -5. Implementing the GTS Reset Sequencer Intel FPGA IP
Reset Release	Notifies that the FPGA logic has entered user mode.	Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs -4. Including the Reset Release IP in Your Design

1-3. Working Environment

The tool used is as follows.

Quartus® Prime Pro Edition v25.1

Furthermore, the created design will be verified on actual hardware in future articles, using the following development kit.

Agilex™ 5 FPGA E-Series 065B Premium Development Kit

2. Design Creation

2-1. Project Creation

After launching Quartus® Prime Pro Edition, the first task is to create a project. Name the project xcvr_sample_top and select the device "A5ED065BB32AE6SR0".

From File -> New Project Wizard, enter as shown below.

2-2. Launch Platform Designer

Next, launch Platform Designer and create a new system. You can start it from Tools -> Platform Designer or by using the shortcut below.

Name the system to be created xcvr_sample.qsys.

When creating a new system, Clock Bridge Intel FPGA IP (referred to as Clock Bridge) and Reset Bridge Intel FPGA IP (referred to as Reset Bridge) are implemented by default as shown below.

2-3. Clock and Reset Settings

This design uses four clock signals and one reset input, so four Clock Bridge modules need to be implemented. You can add Clock Bridge from the IP catalog, but since one is already implemented, here we will duplicate it.

Select the Clock Bridge, right-click, and choose Duplicate. Repeat this three times.

When duplicating, the screen below appears. Since each clock setting differs in this design and the IP Variant file will be set separately, select [Yes].

After this, the left side should look like the figure below. Now rename each module. Select the module, right-click -> Rename to change the name. This time, use the names shown on the right side of the figure below.

Along with renaming the modules, rename the setting files (.ip extension) accordingly. Select the module, right-click -> Rename IP Variant File, and enter the new file name. Use the following names this time.

Reference: Each pane in Platform Designer can be maximized by double-clicking its tab, and restored by double-clicking again.

Reference: If the layout display becomes corrupted, select View -> Reset to System Layout to restore the default layout.

Reference: It is recommended to save your work periodically.

Next, configure the external pins. Set the Export column as shown below. Since clk_100m and clk_156m are inputs from outside, set them as in_clk. Since tx_clkout and rx_clkout are outputs to outside, set them as out_clk.

2-4. Transceiver Settings

In the IP catalog filter box, type "direct" and select the GTS PMA/FEC Direct PHY Intel FPGA IP.

2-4-1. Common Datapath Options

Set the Common Datapath Options here.

This time, use 1 transceiver channel in Duplex mode with a PMA data rate of 17031.25 Mbps, so set as follows.

2-4-2. TX Datapath Options Tab

Next, set the TX Datapath options as shown below.

2-4-3. RX Datapath Options Tab

Set the RX Datapath options as shown below.

2-4-4. FEC Options Tab

Since FEC is not used, set as follows.

2-4-5. PCS Options Tab

Since PCS is not used, set as follows.

2-4-6. Avalon Memory-Mapped Interface Tab

Since we will use the debug function of GTS Direct PHY later, set as follows.

2-4-7. Example Design Tab

Do not generate the Example Design; leave it at the default setting.

2-4-8. Analog Parameters Tab

Leave at the default settings.

2-4-9. Check Message Display

After setting parameters, confirm that there are no Errors or Warnings in Parameterization Messages. If Errors or Warnings appear, the message content will be displayed; review and correct as needed.

After confirming, click the Finish button. This will implement the GTS Direct PHY in Platform Designer.

2-5. Reset Sequencer Settings

From the IP catalog, select "GTS Reset Sequencer Intel FPGA IP." Set as shown below and click Finish. This will implement the GTS Reset Sequencer IP in Platform Designer.

2-6. Reset Release Settings

From the IP catalog, select "Agilex Reset Release IP." Set as shown below and click Finish. This will implement the GTS Reset Release IP in Platform Designer.

2-7. Rename Modules and IP Variant File Names

Rename each module and change the IP Variant File names. This time, change them as shown below.

2-8. Clock Frequency Settings

Set the frequency of each Clock Bridge module. The settings are as follows.

Module Name	Frequency
clk_100m	100 MHz
clk_156m	156.25 MHz
tx_clkout	266.113281 MHz
rx_clkout	266.113281 MHz

To change parameters, select the module, right-click -> Edit Parameters. Enter the frequencies above in the Explicit clock rate field for each module. For 100 MHz, you can enter "100M".

Note that the tx_clkout and rx_clkout frequencies (266.113281 MHz) are the tx_clkout and rx_clkout frequencies of the GTS Direct PHY IP, displayed in the Tx Datapath Options tab and Rx Datapath Options tab respectively. The figure below shows the tx_clkout frequency display.

2-9. Clock Connections

First, connect clocks and resets. From the Current Filter dropdown menu at the bottom center of the screen, select Clock and Reset Interfaces. This will display only clocks and resets.

Connect clocks and resets as shown below.

2-10. Connections of Each Module

Next, connect other signals. Set Current Filter to "All Interfaces" to display all signals.

The signals to connect between blocks this time are only four between GTS Direct PHY and Reset Sequencer.

For unconnected ports, export them as shown below. Double-click the Export column to display the default name. Some interfaces not exported are unused this time, so no problem. Be sure to export reset_release as well.

If a warning "System Information doesn't match requirements of IP" appears in the message window, synchronization is necessary.

There are several methods, but this time select File menu -> Refresh and Reload All Components. Choose "Yes" for "Save?" and when "completed successfully" appears, click "Close".

Warnings like the following will appear, but you can safely ignore them this time.

Keep Platform Designer open and do not generate yet.

3. HDL Generation

3-1. Confirm Registered Files

Keep Platform Designer open and switch to the Quartus® Prime Pro Edition window.
If you changed the IP Variant File name, the old file might still be registered in the project, which can cause errors. Remove these.

Open Project -> Add/Remove Files in Project..., remove files with a question mark, then click Apply. After that, click OK to close.

3-2. HDL Generation

Run Generate HDL to create synthesis and simulation designs. Choose Verilog for HDL this time. Select the simulator according to your environment (Questa is used here).

Confirm that Generate completes without errors and click Close.

3-3. Testbench Generation

Run Generate Testbench System to create the testbench. For Create testbench Platform Designer system, select "Simple BFMs for clocks and resets."