Introduction
Hello, my name is Nami. My name is Nami, and I've been feeling a little bit of growth lately.
This time, I would like to introduce new features of our latest device, Stratix® 10 FPGA.
Stratix 10 has many new features that can improve the overall performance of your design!
We will be introducing these features over the next few issues, so please check back soon.
Meet Hyper-xx
＝At a meeting one day
Section Manager "Regarding Stratix 10's HyperFlexTM, ......, Hyper-Retiming is now available at ...... with the addition of Hyper-Register."
I said "(......Hyper ? )"
Chief "Hyper-Pipelining is .........."
I "......................"
Chief "Hyper-Optimization is ............."
I "How many Hyper-XX's are there..."
Hyper-xx is a lot....
The meeting ended without me being able to distinguish between them.
I thought this was a bad idea, so I went back to my seat and immediately looked them up.
By the way, I recognized Hyper-xx as
HyperFlex
Hyper-Register
Hyper-Retiming
Hyper-Pipelining
Hyper-Optimization
Hyper-Optimization. Let's take a look at what each of them represents.
What is HyperFlex?
HyperFlex is an overall mechanism to improve FPGA performance.
This is a mechanism added since Stratix 10.
And the actual function to improve performance is the above-mentioned "Hyper-Retiming".
Hyper-Retiming
Hyper-Pipelining
Hyper-Optimization
Hyper-Retiming, Hyper-Pipelining, Hyper-Optimization, etc.
Why are these new features available in Stratix 10?
Yes, they are. It is because of a newly added register!
That is Hyper-Register!
What is Hyper-Register?
Hyper-Register is a new register added to Stratix 10.
It is a simple 1-input, 1-output register with the same basic functionality as the ALM register.
There are many Hyper-Registers in Stratix 10. (More than ten times as many as ALM registers!).
) What is noteworthy is the location of the Hyper-Registers.
This is the point where the above new functions can be achieved.
Location of Hyper-Register
Now, where is the Hyper-Register located?
This register is located on the wiring that connects ALMs.
To be precise, it is located at
- Routing Matrix (Row/Column) intersection
- Inputs of all blocks
Let's take a look at this image compared to the inside of a conventional FPGA.
Figure 1: Conventional FPGA Internal Image
Figure 2: Stratix 10 internal image
This is how they are arranged inside.
What is ALM?
As a supplement, let me explain a little about ALM.
ALM is one of the smallest logic units in FPGA and consists of the following.
LUT (look-up table)
- Adder
- Register
The FPGA combines the ALMs to implement the circuits described by the user.
Figure 3: ALM Image Diagram
Stratix 10 has both registers and Hyper-Register in the ALM.
Summary
Stratix 10 provides the flexibility of Hyper-Register and the ability to use the Hyper-Retimed Register.
Hyper-Retiming
Hyper-Pipelining
Hyper-Optimization
Hyper-Register is a new feature in Stratix 10 that allows for flexible and efficient use of the Hyper-Register and improves performance!
HyperFlex
The entire mechanism to improve FPGA performance introduced in Stratix 10.
Hyper-Retiming, Hyper-Pipelining, Hyper-Optimization, etc.
Functions that actually work to improve performance.
Hyper- Register
A register introduced in Stratix 10 to realize the above functions.
There are many Hyper -xx in this article, and there was a lot of confusion while writing this article....
However, we will try our best to make the article easy to understand so that everyone can understand it!
In the next article, we will introduce one of the new features, Hyper-Retiming!
So, how exactly Hyper-Register works will be revealed!
Check it out!