Introduction
Hello, my name is Nami!
In the last issue, I wrote an article about Hyper-Register, a new mechanism to realize Stratix® 10 FPGA's HyperFlexTM .
This time, I would like to continue the article.
Let's review Hyper-xx just in case....
Hyperflex™
The whole mechanism to increase FPGA performance introduced in Stratix® 10 FPGA.
Hyper-Retiming, Hyper-Pipelining, Hyper-Optimization, etc.
Functions that actually work to increase performance
Hyper-Register
A register introduced in Stratix® 10 FPGA to realize the above functions.
This time, I will write about one of the functions, Hyper-Retiming!
If you haven't read the previous article yet, please do so!
[Stratix 10 New Feature - The Mystery of Hyper-XX: What is Hyper-register?]
If you haven't read the previous article yet, please read [Stratix 10 New Feature - Mystery of Hyper-XX (What is Hyper-register?)] before reading this article.
Before talking about Hyper-Retiming, let's talk about the existing Retiming feature...
What is Retiming?
Retiming is a Quartus® Prime feature that improves performance by balancing delays between ALM registers and eliminating critical paths .
Figure 1: Retiming Imagery
As shown in Figure 1, by moving registers without changing the logic functions, delays on paths that do not meet timing requirements can be reduced.
In addition, if the routing delay is long, the register can be moved to shorten the delay.
Example:
Suppose you want the FPGA to operate at 300 MHz (3.3 ns ).
In this case, data must propagate between ALM registers within 3.3ns .
Suppose now that the ALMs are connected as shown in the diagram in Figure 2.
Figure 2: Placement and wiring that does not meet the desired operating frequency
The delay between each register is 1.5ns and 3.5ns.
In this case, 3.5ns delay is generated and the operating frequency is 286MHz , which does not satisfy the desired operating frequency ( 300MHz ).
In this case, the Retiming function is used!
Specifically, it improves timing by utilizing unused ALM registers that are located in positions that can be optimized for the critical path.
Figure 3: Placement and routing that satisfies the desired operating frequency by Retiming
In this way, they are adjusted to meet the desired operating frequency (Figure 3).
In the above example, we were able to improve the timing, but if the resource utilization is high and many ALMs are already in use, the timing may not be improved.
Also, there may be a desire to increase the operating frequency.
This is where Hyper-Retiming with Hyper-Register comes in!
What is Hyper-Retiming?
Hyper-Retiming is a function thatuses
Hyper-Register to balance routing delays between registers to eliminate critical paths and
improve operating frequency (performance).
Hyper-Retiming can be done in two ways.
[1] Improve performance by changing only the placement of registers
[2] Improve performance by also changing the combinational circuitry and register order
[1] Improve performance by changing only the placement of registers.
Figure 4 shows how Hyper-Register can be used.
Figure 4: Hyper-Registering
Unlike the previous example, we use Hyper-Register on the wiring.
As a result, the conventional Retiming can run at 333MHz after the improvement, but with Hyper-Retiming , it can run at 400MHz!
As I wrote in the previous article, Hyper-Register is very richly arranged, so we can use Hyper-Register at just the right position.
So the timing improvement is higher than before!
Furthermore, Hyper-Registers are placed separately from ALM registers, so even if all ALMs are used, they can be retimed!
[2] Performance can be improved by changing the order of combination circuits and registers.
The Hyper-Retiming function can also improve performance by changing the order of combination circuits and registers.
For example, if the two-stage LUT does not meet timing requirements, performance can be improved by moving a register between the two LUTs.
Retiming moves a register upstream of the logic and is called Backward Retiming, while moving a register downstream of the logic is called Retiming moves a register upstream of the logic, which is called Backward Retiming.
The advantage of this function is that it improves performance while maintaining functionality.
As shown in Figure 5 and Figure 6, moving registers before or after the combinational circuit reduces delay.
Figure 5: Backward Retiming
Figure 6: Forward Retiming
Hyper-Register functions by taking advantage of this flexibility!
However, there is a caveat to Hyper-Register...
Cautions when using Hyper-Retiming
Hyper-Retiming is very convenient, but there are some precautions that must be taken when using it.
For example, when using asynchronous clear, Retiming may not work or initial values may not be maintained.
For this reason, we have summarized the cases where Hyper-Retiming is not enabled.
The areas where Retiming is not possible
- Asynchronous cleared registers
- Synchronizerchain
- Registers at I/O boundaries (Virtual pin settings are similar)
- Paths between asynchronous clock domains
- Registers specified as destinations in SDC constraints
- Synt hesisRegisters for which the attribute "preserve" is declared
- RAM/DSPs block
- Latch
For details, please refer to "Facilitate Register Movement (Hyper-Retiming)" in the following document.
Even if Hyper-Register is not enabled and no performance improvement is achieved, you can check what the bottleneck is with Quartus Prime so that you can take countermeasures!
Stratix 10 High-Performance Design Handbook:
Also, if you are interested in learning more about Hyper-xx, please click here.
Summary
Advantages of Hyper-Retiming
1. Higher timing improvement rate due to more flexible placement than ALM registers
2. Timing improvement independent of ALM utilization
The remaining functions we plan to write about in the article are
- Hyper-Pipelining
- Hyper-Optimization
The next article will be about Hyper-Pipelining.
Please look forward to it!
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