Introduction
Field Programmable Gate Arrays (FPGAs) are flexible devices that allow users to freely define circuit configurations. However, due to this characteristic, nothing works immediately after power-on; in order for an FPGA to function, an initialization operation called "configuration" must first be performed to write the designed circuit data (configuration data) to the device.
In this article, we will show you how to perform configuration using Agilex™ 3 FPGA as an example.
Point: Although Agilex™ 3 is used as an example, this procedure is common to other device families that use Secure Device Manager (SDM), such as the Agilex™ family and Stratix® 10. The following procedure is common to all families of devices that use Secure Device Manager (SDM), such as the family and Stratix® 10 devices.
1. configuration method selection (MSEL)
There are three configuration schemes that can be selected in Agilex™ 3. Which mode is used is determined by the status of the three FPGA pins called MSEL.
[Table 1] List of Configuration Methods
| Scheme | Description | MSEL[2:0] (1:0) |
| JTAG configuration | A mode in which configuration data is poured directly into the FPGA over the JTAG interface. Useful when frequently changing FPGA circuit data during debugging. | 111 |
| AS (Active Serial) configuration | A mode in which the FPGA accesses the Serial Flash ROM (QSPI Flash) to configure itself. This is the most common way to have the FPGA perform configuration automatically after power-on. |
001 (Fast mode) 011 (Normal mode) |
| AVST (Avalon-ST) configuration | Configuration from a master device (CPLD, MCU, etc.) connected to the FPGA via an 8-bit or 16-bit parallel bus. |
101 (x16) 110 (x8) |
Reference: Device Configuration User Guide Agilex™ 3 FPGAs and SoCs
Point: AVST configuration is a new scheme added for SDM-equipped device families; JTAG and AS configurations are also available for non-SDM device families.
From here, we will introduce how to write configuration data. This article does not cover the AVST configuration, since the configuration data management is done on the master device side. 2.
2. Configuration Procedure (Quartus Programmer)
This section describes the steps from starting the Quartus Programmer to writing configuration data, which is basically the same for both JTAG and AS configurations, although the target files are different.
Point: The file format for writing is different between JTAG config and AS config: JTAG config uses .sof or .rbf files, while AS config uses .jic files.
2-1. start the tool
The tool can be started from the Start menu on Windows, or by executing "quartus_pgmw" in a terminal under the Quartus path on Linux.
[Figure 1] Tool startup
2-2. device detection (Hardware Setup ~ Auto Detect)
Click the Hardware Setup button to specify the JTAG hardware and clock frequency to be connected. Click the Auto Detect button.
[Figure 2] Device Detection
2-3. file and operation selection
With the Auto Detect device selected, click the Change File button to select the file to be written. Then, check the Program/Configure checkbox for the device to be written.
Point: There is a difference in the device displayed when selecting .sof/.rbf for JTAG configuration and when selecting .jic for AS configuration. In the case of writing to Flash, you can also select "Verify" after writing to Flash.
[Figure 3] File and Operation Selection
2-4. Writing Execution
Click the Start button to start writing. When the progress bar in the upper right corner displays "100% (Successful)," the writing is complete.
[Figure 4] Writing Execution
This is the end of the configuration procedure using the Quartus Programmer. 3.
3. Application: Using the Command Line Tool
For users who find it tedious to run the Quartus Programmer each time, this section introduces a command line method. This is especially useful for users who repeatedly debug using the JTAG configuration.
A tool called quartus_pgm is available as a command line version of the Quartus Programmer tool introduced in the first section. This tool is used by entering commands on a terminal with a Quartus Prime path, such as the Nios V Command Shell.
Point: If you save frequently used commands as text, you can save time by simply starting the terminal and copying and pasting the command sequence to perform configuration. 3-1.
3-1. basic usage
Point: When using in a Windows environment, enter the command as quartus_pgm.exe (with extension).
Basic syntax:
quartus_pgm -c <cable number> -m <mode> -o <operationVerify JTAG connection1 (displays list of cable numbers):
quartus_pgm -lJTAG connection check 2 (displays a list of devices connected to the cable): quartus_pgm -c
quartus_pgm -c <cable number> -a
[Table 2] Frequently used options for quartus_pgm
| Option | Description |
| -l | Display a list of connected cables |
| -c <cable number | Specifies the cable to use (e.g., -c 1) |
| -m <mode | Specify configuration scheme (e.g. jtag, as) |
| -o <operation |
Operation to perform (e.g. -o "P;filename.sof@1")
@1 is the number of the device displayed in the JTAG chain (in order of appearance) (@1 if the target appears first in the chain) |
| --help or -h | Display help |
3-2. Execution example (JTAG mode: writing .sof file)
The following is an actual command line for configuration in JTAG mode.
quartus_pgm -c 1 -m jtag -o "P;filename.sof@1" Note: Only the following display example is shown with an Agilex™ 5 device, but it is the same for Agilex™ 3.
Terminal display at runtime:
[Figure 5] Confirmation of cables and devices to be connected.
[Figure 6] Device display after writing is executed and completed (if HPS exists)
Note: When using a design that includes a Hard Processor System (HPS), an ARM SoC device is added to the JTAG chain when the initial configuration is complete and the HPS starts booting. Note that the device number specified at the end of the -o option must be changed to @2 the first time and the second time thereafter.
Conclusion
In this article, we introduced the FPGA configuration method using the Quartus Programmer, and we hope that by understanding the configuration operation from both the GUI tool and the command line, you will be able to choose the method that is easiest to use for your application.
Configuration is the first step in running an FPGA. Now that you understand configuration, you are ready to try running Agilex™ 3 and other FPGA reference designs.
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