Getting Started with Transceivers: Agilex™ 5 / Agilex™ 3 Edition, Basics Part 3 - Actual Hardware Operation Verification – Macnica Altera FPGA Insights

Introduction

This article is the Basics Part 3 of the "Getting Started with Transceivers Agilex™ 5 / Agilex™ 3 Edition." It covers creating a design for actual hardware verification from the designs and test benches made in Basics Parts 1 and 2, and performing operation verification.

Note: If you skip Basics Part 2 and start working from this article, please use the files attached at the end of this article. Refer to the following for the files to use and the chapter to start from.

#	Task	Files to Use	Chapter to Start From
1	When performing various settings in this article	xcvr_sample_top_basic_3_start_v251.7z xcvr_sample_top_basic_3_start_v261.7z	1-2. Overview of Changes
2	When using the pre-configured files in this article and only performing hardware verification	xcvr_sample_top_basic_3_end_v251.7z xcvr_sample_top_basic_3_end_v261.7z	1-9. Running Full Compilation

The block diagram of the design to be created is as follows.

1. Preparing the Design for Hardware Verification

1-1. Creating the Design for Hardware Verification

Reuse the test bench created in Basics Part 2 to create the design for hardware verification.
The test bench file is as follows:
File path: (project folder)\xcvr_sample_tb\xcvr_sample_tb\sim
File name: xcvr_sample_tb.v

Edit this file to create the design for hardware verification. Please follow these steps:
(1) Copy xcvr_sample_tb.v to the project folder
(2) Rename the file to xcvr_sample_top.v

1-2. Overview of Changes

Modify the copied xcvr_sample_top.v in the project folder for hardware verification. The main changes are the following three points:
(1) Change the module name to match the file name change (xcvr_sample_tb - xcvr_sample_top)
(2) Add declarations for input/output ports
(3) Remove unnecessary BFM descriptions and internal signals

1-3. Declaration of Input/Output Ports

Add declarations for input/output ports to the test bench created in Basics Part 1. The added ports include clock, reset, serial ports, and also RX parallel data. This is to prevent the design from being removed during logic synthesis. During compilation, these will be set as Virtual Pins so they do not become actual output pins.

The declaration looks like the following. Since the reset on the development kit is active low, the signal name is reset_reset_n and is inverted internally for connection.

module xcvr_sample_top (
    input  wire        clk_100m_clk,
    input  wire        clk_156m_clk,
    input  wire        reset_reset_n,
    output wire        o_tx_serial_data,
    output wire        o_tx_serial_data_n,
    input  wire        i_rx_serial_data,
    input  wire        i_rx_serial_data_n,
    output wire        rcvd_data_valid,
    output wire [31:0] rcvd_data_32b_hi,
    output wire [31:0] rcvd_data_32b_lo
    );
    
wire       reset_reset = ~reset_reset_n;

1-4. Deleting Unnecessary Descriptions

Since the clock and reset inputs become external pins, BFM is no longer needed. Also, internal signals become input/output signals and should be commented out.

Additionally, comment out the loopback description as well.

With this, the design creation is complete.

1-5. Running Compilation

Compile the design created in 1-3 with Quartus Prime. First, execute IP Generation and Analysis & Synthesis. Before running, please check the following:
(1) "xcvr_sample_top" is selected in the Project Navigator
(2) In Project - Add/Remove Files in Project, the files are displayed as shown below

If "?" appears as shown below in (2), please remove these files (select and click Remove, then click Apply).
If there is no "?" displayed, no action is needed.

After confirming the above, first execute IP Generation, then Analysis & Synthesis. You can run them by clicking the buttons below.

If completed successfully, the following message will display. Then click OK.

1-6. Setting Pin Assignments, IO Standards, and Virtual Pins

Open the Assignment Editor from Quartus Prime's Assignments - Assignment Editor. Set as shown below.

The above can be set individually in the Assignment Editor, or you can copy the following text into xcvr_sample_top.qsf to configure it.

set_location_assignment PIN_BC29 -to clk_156m_clk -comment IOBANK_4A
set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to clk_156m_clk -entity xcvr_sample_top

set_location_assignment PIN_BK109 -to clk_100m_clk -comment IOBANK_5B
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to clk_100m_clk -entity xcvr_sample_top

set_location_assignment PIN_BR112 -to reset_reset_n -comment IOBANK_5B
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to reset_reset_n -entity xcvr_sample_top

set_location_assignment PIN_BY7 -to o_tx_serial_data -comment IOBANK_4A
set_location_assignment PIN_CB1 -to i_rx_serial_data -comment IOBANK_4A
set_location_assignment PIN_BY10 -to o_tx_serial_data_n -comment IOBANK_4A
set_location_assignment PIN_CB3 -to i_rx_serial_data_n -comment IOBANK_4A
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to o_tx_serial_data
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to i_rx_serial_data
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to o_tx_serial_data_n
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to i_rx_serial_data_n

set_instance_assignment -name VIRTUAL_PIN ON -to rcvd_* -entity xcvr_sample_top

Also, add the OSC_CLK frequency and other settings to the qsf file according to the development kit. Copy the following into xcvr_sample_top.qsf.

set_global_assignment -name USE_CONF_DONE SDM_IO12
set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_125MHZ

Note: From Quartus® Prime Pro Edition 25.1.1 onward, specifying Location and I/O Standard for I/O pins is required to generate programming files. If the necessary assignments are not made, programming files will not be generated. Please also refer to the following FAQ.
Programming files are not generated when compiling with Quartus® Prime Pro Edition 25.1.1.
Also, I/O pins without necessary assignments can be checked in the compile report under I/O Assignments Warnings.

1-7. Setting Timing Constraints

Next, create an sdc file to set timing constraints. This time, only clock constraints and paths that do not require analysis will be set.

From Quartus File - New, select "SDC File (Read by the Timing Analyzer at each fitter stage)".

Copy the following into the opened file and save it as xcvr_sample_top.sdc (Files - Save As...).

create_clock -name clk_100m -period 10 [get_ports clk_100m_clk]
create_clock -name altera_reserved_tck -period 40 [get_ports altera_reserved_tck]

set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]

set_false_path -from [get_keepers {xcvr_sample_inst|phy|*}] -to [get_keepers {s_xcvr_tx_ready_2r[0]}]

Open Project - Add/Remove Files in Project and confirm that the saved xcvr_sample_top.sdc has been added. Use the Down button to move this file to the bottom of the list.

Also, open Assignments - Settings, select the Timing Analyzer category, and add xcvr_sample_top.sdc. The screen after adding is shown below. Click OK to close.

Reference: For the order of registering SDC files, please see the following.
Order of registering multiple SDC files in Quartus® Prime development software

1-8. SignalTap Settings

Set up SignalTap to check internal signals. Select Tools - Signal Tap Logic Analyzer in Quartus Prime. Selecting the default screen opens the following window.

Configure as shown below.

After setting, name and save the file. The default name is stp1.stp (numbers increment sequentially). When prompted with "Do you want to enable Signal Tap File ....", select "Yes".

Close the SignalTap window, open Assignments - Settings in Quartus Prime, select Signal Tap Logic Analyzer category.
Confirm SignalTap is enabled and the created file name is selected, then click OK to close.

1-9. Running Full Compilation

With the above settings complete, run a full compilation to generate the programming file.

You can run full compilation using the shortcut below.

After successful compilation, the following message appears. Click OK to proceed. Timing analysis will then run automatically.

When timing analysis runs, the following appears. Unconstrained Paths remain, but since the purpose here is only to verify the transceiver part, Unconstrained Paths are temporarily ignored.

1-10. Checking Compilation Results

After compilation, confirm that pin assignments are properly set and that the programming file is generated. Click the shortcut below to open the report.

Select Input Pins and Output Pins respectively and verify that Pin# and I/O Standard are correctly set.

Next, verify that the programming file is generated. Confirm that xcvr_sample_top.sof is created in the output folder of the project folder.

(In ver25.1.1, I/O Standard .... sof may not be generated, so please check settings and run back annotation.)

2. Hardware Verification

2-1. Preparing the Development Kit

Connect the SMA connectors of Altera's Premium Kit as TX1_P/TX1_N and RX1_P/RX1_N.

2-2. Programming the Device

Write the generated programming file to the FPGA. This time, programming will be done via SignalTap.

With the development kit powered on, launch Signal Tap Logic Analyzer from Tools and configure as follows:
(1) Select Hardware: Agilex 5E065B Premium DK
Device: @2 : A5E (C065BB32AR0....)
(2) Select xcvr_sample_top.sof
(3) Click to start programming

2-3. Waveform with SignalTap

After writing the programming file (.sof), start measurement using the shortcut below.

The display will look as shown below.

Expanding rcvd_data_32b_hi[31:0] and rcvd_data_32b_lo[31:0] shows a 10-bit counter waveform. Alignment has not been performed this time, so the position of bit 0 of the counter is not aligned.
The transmitted pattern stacks six 10-bit counters and one 4-bit counter vertically to make 64 bits, so the highest bits form a 4-bit counter.

Below is an example where the highest 4-bit counter is rcvd_data_32b_lo[23:20].

If the display looks like a counter for now, that is fine. The method for bit alignment and other details will be prepared in a separate article.

Reference: The transmitted data is 64 bits, consisting of six 10-bit counters and one 4-bit counter. Since alignment is not done this time, the position of bit 0 in the 64-bit data is shifted. In this example, rcvd_data_32b_lo[24] became bit 0 of the 64-bit data.

Conclusion

This concludes this article. Please continue to Basics Part 4 - Transceiver Toolkit (coming soon).