Introduction
There are two clock modes for the internal datapath clocks of Agilex™ 5 / Agilex™ 3 transceivers: PMA Clocking Mode and System PLL Clocking Mode. This article explains these two clock modes.
1. Transceiver Block Diagram
Figure 1 shows the overall block diagram of the Agilex™ 5 / Agilex™ 3 transceiver and the PMA block diagram. The main components are PMA, Hard IP (FEC, PCS, Ethernet MAC, PCIe Hard IP), System PLL, and Reference Clock Network. Additionally, the PMA implements a TX PLL for transmission and an RX PLL (CDR) for reception.
Inside the transceiver, besides the TX PLL and RX PLL, there is a System PLL implemented. The purpose of this System PLL is for calibration (correction of individual device variations) and supplying clocks to the internal datapath of the transceiver. This role differs from that of the TX PLL and RX PLL, which handle serial data processing.
Here, the mode that uses the PMA output clocks (TX PLL and RX PLL output clocks) for the internal datapath clocks of the transceiver is called PMA Clocking Mode, and the mode that uses the System PLL output clocks is called System PLL Clocking Mode.
For more details on the block diagram, please also refer to the following chapters.
2.1. Building Blocks
2.3. PMA Architecture
Figure 1 Overall block diagram of Agilex™ 5 / Agilex™ 3 transceiver and PMA block diagram
2. About PMA Clocking Mode and System PLL Clocking Mode
2-1. Supported Configurations for Each Mode
The supported configurations for PMA Clocking Mode and System PLL Clocking Mode are as shown in the table below.
Table 1 Supported Configurations for PMA Clocking Mode and System PLL Clocking Mode
Configuration |
PMA Clocking Mode |
System PLL Clocking Mode |
PMA Direct Mode |
〇 |
〇 |
PCS Direct Mode |
× |
〇 |
FEC Direct Mode |
× |
〇 |
Use of Ethernet MAC |
× |
〇 |
Use of PCIe Hard IP |
× |
〇 |
Dynamic Reconfiguration |
× |
〇 |
PMA Clocking Mode can only be configured in PMA Direct Mode. On the other hand, System PLL Clocking Mode supports all configurations. Please also refer to the following link.
2.6.2. Datapath Clock Network
Note that the design created in Getting Started with Transceivers Agilex™ 5 / Agilex™ 3 Edition, Basics Part 1 - Design Creation uses PMA Clocking Mode.
2-2. About the Internal Datapath Clocks of the Transceiver
This section explains the internal datapath clocks of the transceiver in PMA Clocking Mode and System PLL Clocking Mode.
The datapath from the PMA to the FPGA Core Interface (tx_parallel_data / rx_parallel_data) includes PMA Interface FIFO and Core Interface FIFO.
Between PMA and FEC: PMA Interface FIFO
Between EHIP MAC and FPGA Core Interface: Core Interface FIFO
Here, the mode that uses PMA output clocks for each FIFO and datapath is called PMA Clocking Mode (Figure 2), and the mode that uses System PLL output clocks is called System PLL Clocking Mode (Figure 3).
The figures below highlight the clock lines based on the figures from the user guide at the following link.
3.1. IP Overview
Figure 2 Clock Configuration in PMA Clocking Mode
Figure 3 Clock Configuration in System PLL Clocking Mode
The configurations of each FIFO are also noted in the above figures, but for details, please check the links below.
3.1.1. PMA Direct Supported Modes
3.1.2. FEC Direct Supported Modes
3.1.3. PCS Direct Supported Modes
2-3. Recommended Settings for tx_clkout / rx_clkout and tx_coreclkin / rx_coreclkin
In the FPGA Core Interface of Figures 2 and 3, the clock output ports from the transceiver are tx_clkout / rx_clkout. From the transceiver’s perspective, the clocks connected to the Core Interface FIFO inputs are tx_coreclkin / rx_coreclkin. The recommended settings and connection methods for these clocks are shown in Table 2. Please also refer to the following link.
3.7.2. Recommended tx/rx_coreclkin Connection and tx/rx_clkout2 Source
Table 2 Recommended Settings for tx_clkout / rx_clkout and tx_coreclkin / rx_coreclkin
| Datapath Clocking Mode | Core Interface FIFO Mode | Single/Double Data Width Transfer |
Recommended tx/rx_coreclkin Connection |
Recommended tx/rx_clkout source |
Recommended tx/rx_clkout2 source |
Division Factor |
| PMA Clocking Mode | Phase Compensation | Single Width | o_tx/rx_clkout | Word clock | (None) |
N/A |
| Double Width | o_tx/rx_clkout2 | Word clock | (None) |
2 | ||
| Elastic | Single Width | o_tx/rx_clkout or other user clock | Word clock / user clock | (None) |
N/A | |
| Double Width | o_tx/rx_clkout2 or other user clock | Word clock / user clock | (None) |
2 | ||
| System PLL Clocking Mode | Phase Compensation | Single Width | o_tx/rx_clkout | System PLL clock | Word clock |
N/A |
| Double Width | o_tx/rx_clkout | System PLL clock | Word clock |
2 |
2-4. Clocking Mode and Cadence
In System PLL Clocking Mode, since the System PLL output clock is used for the internal datapath clocks of the transceiver, data handoff occurs between this clock and the PMA output clock. If these two clocks have the same frequency and zero offset (0 ppm), it is called standard cadence, where data is valid every clock cycle. If the frequencies differ or there is a frequency offset, it is called custom cadence, and in this case, data is not valid every clock cycle, and there are timings when data is invalid. Therefore, to identify invalid timings, the TX side must enable Custom Cadence during IP generation to create the tx_cadence port. The RX side should use the data valid bit.
Please also refer to the following link.
2.6.4. Datapath Clock Cadences
Table 3 Clock Mode and Cadence
| Datapath Clocking Mode | Configuration | Frequency of System PLL Clock and PMA Clock | Cadence |
| PMA clocking mode | PMA Direct | System PLL Clock not used |
standard cadence (Data valid every clock cycle) |
| System PLL clocking mode | PMA Direct | System PLL Clock and PMA Clock have the same frequency with zero offset (Δppm=0) |
standard cadence (Data valid every clock cycle) |
| Others | custom cadence |
In the case of custom cadence, please check the following settings for TX. This will generate the tx_cadence port, which should be used as the valid timing for tx_parallel_data in the FPGA Core Interface. For example, it can be used as a read request signal for a FIFO.
For RX, please use the data valid bit of rx_parallel_data to detect valid data timing. For the mapping of the data valid bit, please refer to the following.
3.6. Bit Mapping for PMA, FEC, and PCS Mode PHY TX and RX Datapath
2-5. User Circuit Interface in System PLL Clocking Mode
The following is an example configuration for custom cadence in System PLL Clocking Mode. In the FPGA Core Interface, tx_clkout / rx_clkout are in the clock domain generated by the System PLL. According to Table 2, the recommended connection for tx_coreclkin / rx_coreclkin in System PLL Clocking Mode is tx_clkout / rx_clkout. When connected this way and operating the user circuit with this clock, it is as shown in Figure 4. On the other hand, if the user circuit operates with the PMA output clock (generated by TX PLL and RX PLL) in System PLL Clocking Mode, it is recommended to output the PMA output clock as tx_clkout2 / rx_clkout2 and insert a DC FIFO as shown in Figure 5.
Figure 4 Example of operating the user circuit directly with the System PLL output clock
Figure 5 Example of operating the user circuit with the PMA output clock, inserting a DCFIFO
Conclusion
This concludes the article. We hope you appropriately select and handle the two transceiver clock modes according to the clock configuration and intended use.