Introduction
In this chapter, you will learn Signal Tap Logic Analyzer through a real device.
Signal Tap Logic Analyzer is a powerful tool for real-time debugging in FPGA development.
Directly observe signals inside the FPGA and capture events with complex trigger conditions.
GUI-based operation allows designers to efficiently and intuitively identify and analyze problems.
Bugs that are often missed in simulation can be caught reliably with the Signal Tap Logic Analyzer.
In this article, we will show you how to use SignalTap step-by-step, using a pre-prepared QSF file (Quartus Settings File), Verilog file, and Signal Tap Logic Analyzer Settings File (STP).
Downloadable files are available from the bottom of this page.
1. environment setup
First, download the QSF, Verilog source files, and STP files and store them in a folder of your choice.
Select an arbitrary folder from the New Project Wizard in the File menu of the Quartus® Prime menu bar as shown below and name the project
"signaltap_demo".
Select Next and you will be prompted to select a device.
Select Agilex 3 (C-series) as the device and enter "A3CZ135BB18AE7S" in the filter field.
Since we will be using the Terasic Atum A3 Nano Kit, the pin numbers in the qsf file will also match the board shown above.
However, it is possible to use other devices, evaluation kits, or your own environment by changing the devices and pin numbers used.
Once the project is created, simply click the blue triangle compile button to complete the design preparation. 2.
2. design description
This circuit is a simple circuit consisting of a 32-bit counter running at a 50 MHz clock and a 4-bit counter that counts up each time a button on the board is pressed. 3.
Operation of Signal Tap Logic Analyzer
After compilation, select "Signal Tap Logic Analyzer" from the Tool menu.
Connect the board and PC with USB cable, turn on the power, select Atum A3 Nano [USB-1] from Hardware Setup, and press Close.
(If you are using a different environment, you will see a different board name or download cable name, so select the appropriate one.)
Select the sof file and press the "Program Device" button to write the file.
The Signal Tap Logic Analyzer is now ready to use.
With "auto_signaltap_0" highlighted, press the Run analysis button.
You will see that the 32-bit counter is counting up each time you press the Run analysis button.
Run analysis button, 1st time
Run analysis button, second press
You will see that the 32-bit counter is constantly counting up.
The Run analysis button allows you to manually capture waveforms one at a time, while the adjacent Autorun analysis button automatically repeats each trigger and keeps updating the waveforms.
By the way, in Signal Tap Logic Analyzer, even if you do not explicitly set the trigger condition, the condition is satisfied by default when any signal change occurs.
Let's change the trigger conditions here:
Switch to the Setup tab, right-click on the Trigger Conditions column of the push_button, and select Falling Edge.
When triggered by Autorun analysis, the trigger condition is satisfied and the waveform is updated each time the KEY0 button of the Atum A3 Nano Kit shown below is pressed.
Signal Tap Logic Analyzer allows you to debug invisible signals inside the device by setting arbitrary conditions.
Once you know how to use it, you will be able to use it for debugging.
"When the 32-bit counter reaches 0"
"When the manual counter reaches 10", "When the 32-bit counter reaches 0", etc.
Try changing the trigger conditions, such as "when the 32-bit counter reaches 0" or "when the manual counter reaches 10," and see if you can see the signal you want to see under the desired trigger conditions. 4.
4. conclusion
Signal Tap Logic Analyzer can be used to capture waveforms under complex trigger conditions, at device startup, and to extend the length of captured waveforms.
If you are interested in using the Signal Tap Logic Analyzer for your own design, please refer to the following document, which is available separately and explains it in detail.
FPGA On-Chip Debugging "Signal Tap"
https://www.macnica.co.jp/business/semiconductor/articles/intel/119185/
Quartus Prime First Time Guide to SignalTap Logic Analyzer
https://www.macnica.co.jp/business/semiconductor/articles/pdf/ELS1444_Q1710_10__1.pdf
5. attachments
QSF (Quartus Settings File), Verilog file, and SignalTap configuration file (STP) used in the explanation of this article.
Click here for the full list of the 'Let's Try Agilex™ 3' series.