Introduction
When using field programmable gate arrays (FPGAs), it is often necessary to verify that the device is configured correctly. The "Configuration Debugger" included in the Quartus Programmer is a useful tool for this purpose.
This tool allows you to directly check the FPGA configuration status via JTAG, which is very useful in development and verification.
Although the Configuration Debugger can also retrieve sensor information such as voltage and temperature, this article will focus on how to retrieve configuration information such as configuration mode and status pin states.
Note : The Configuration Debugger is available in Quartus® Prime Pro Edition version 21.3 or later, but not in versions less than 21.3 or in Standard Edition.
Point: Although this article uses Agilex™ 3 as an example, the procedure is the same for other device families that use Secure Device Manager (SDM), such as the Agilex™ family and Stratix® 10. For the device families without SDM, there are some differences in the configuration information that can be obtained, but you can refer to the Configuration Debugger for the procedure.
1. Procedure for obtaining configuration information
This section describes the flow of starting Configuration Debugger from Quartus Programmer to display configuration information.
1-1. Start Quartus Programmer
The Quartus Programmer can be started from the Start menu on Windows, or by executing "quartus_pgmw" on a terminal under the Quartus path on Linux.
[Figure 1] Starting the Quartus Programmer
To check the current configuration status, execute the configuration after the Quartus Programmer is started.
Reference: Please refer to the following contents for the FPGA configuration procedure.
Let's Try Agilex 3 - FPGA Configuration
1-2. Start Configuration Debugger
Select Tools menu -> Configuration Debugger in Quartus Programmer to start Configuration Debugger.
[Figure 2] Startup of Configuration Debugger
1-3. Obtaining configuration information
Perform the following operations on the Configuration Debugger screen.
Click the [Hardware Setup] button and select the hardware configuration to be used for debugging.
If the hardware setup has more than one device, click the [Load Device] button and select a device from the drop-down list.
Click the [Device Info] tab to view device information.
Click the [Read Device Info] button to obtain device information from the selected device.
[Figure 3] Obtaining configuration information
2. Confirming the configuration status
This section describes information that is particularly useful for debugging among the information obtained in the procedure described in section "1-3 Obtaining Configuration Information".
[Figure 4] Confirming the Configuration Status
[Table 1] Items displayed on the Configuration Debugger screen
No. |
Category | Item | Description |
|---|---|---|---|
1 |
Configuratin Status | State | Device configuration status - BOOTROM: Boot ROM running - CONFIG: Configuration in progress - DEVICE CLEAN: Device clean - ERROR: Configuration error occurred - IDLE: Idle state - USER MODE: User logic Running |
2 |
Pin Signals | MSEL | MSEL values latched by the device when power is turned on - b000 - Avalon-ST (x32) - b101 - Avalon-ST (x16) - b110 - Avalon-ST (x8) - b001 - AS (Fast mode for CvP) - b011 - AS (Normal mode) - b111 - JTAG |
3 |
nSTATUS | * See FPGA Configuration Flow below. | |
4 |
nCONFIG | * See FPGA Configuration Flow below. | |
5 |
Soft Function Status | CONF_DONE | Green (HIGH) indicates that all configuration data has been received |
6 |
INIT_DONE | Green (HIGH) indicates that the device has entered user mode after configuration is complete | |
7 |
Configuration Error | Error Message | Error message that corresponds to an error when an error occurs |
8 |
Debug Suggestion | Action to be taken to resolve the error | |
9 |
Major Error Code | Major error codes for configuration-related errors | |
10 |
Major Error Type | Type of error corresponding to Major Error Code | |
11 |
Minor Error Code | Secondary error code for configuration-related errors | |
12 |
Minor Error Type | Error type corresponding to the Minor Error Code | |
13 |
Error Location | Approximate location of the error in the bitstream | |
14 |
Error Detail | Detailed information about where the error occurred |
Reference: The FPGA configuration flow is as follows:
Device Configuration User Guide Agilex™ 3 FPGAs and SoCs - 2.2. Configuration Flow Diagram
[Figure 5] FPGA Configuration Flow
(Source: Device Configuration User Guide Agilex™ 3 FPGAs and SoCs)
Conclusion
The Configuration Debugger allows you to easily check the FPGA configuration status, which is useful for early detection of problems and review of the design. In particular, simply checking the MSEL settings and State status can provide a great hint to determine the success or failure of the configuration.
We hope this article will assist you in your development using Altera® FPGAs.
Click here for the full list of the 'Let's Try Agilex™ 3' series.