Introduction.
Set timing constraints on a simple design and use Timing Analyzer to analyze Fmax and Report Timing.
We will also show you how to change the SDC and analyze it without recompiling.
The design used in this presentation can be downloaded from the bottom of this page.
1. system and rtl
The following figure shows the system and RTL for timing analysis.
The system and RTL are shown in the figure below, without any board delay. 2.
2. HDL and Timing Constraints
HDL and SDC describe RTL.
For more details about SDC, please refer to the following document
Document. 2.4: Timing Constraint Descriptions
For more information on timing constraint methods, please refer to the following article
Reference: Quartus® Beginner's Guide - Timing Constraint Descriptions
3. register SDC file
Register the user SDC file and the IP-generated .ip file created on the following screen in the Assignment menu > Settings.
Point: Registered files are loaded from the top, so it is recommended to register the user SDC file at the bottom.
More details on this page in the following documents and articles
Documentation: 2.2.1. Step 1: Specify General Timing Analyzer Settings
4. Compile and check the configuration with RTL Analyzer
Once compiled, the RTL Analyzer can be checked and the Timing Analyzer analysis is enabled.
In RTL Analyzer, you can check the design with HDL as a block as shown in the figure below.
(Tools → Netlist Viewers → RTL Analyzer (Elaborated))
Reference: Analyzing Design RTL
5. Check Report with Timing Analyzer
Timing Analyzer, which is automatically started after compilation, displays various Timing Summary.
Documentation: 2.5.23. Design Closure Summary
Let's start to generate a concrete report from here.
Click the Clocks folder > Report Clocks in the Tasks pane to see the currently defined clock constraints.
Document: 2.5.6. Report Clocks and Clock Network
1): Definitions constrained by user SDC
2): Clock definitions defined in the .ip file that is automatically generated when the PLL is generated.
The input clock definition from the CLOCK_IN port is automatically defined with the name "PLL0|iopll_0_refclk" in the red frame.
Next, Fmax can be found in the Datasheet folder in the Tasks pane > Report Fmax Summary.
Documentation: 2.5.1. Report Fmax Summary
Next, check the Setup Summary in the Report pane. (Setup Summary is analyzed by default)
There is a timing error in the c1 clock of the PLL, so cross-probing to Report Timing to analyze the details.
Right-click the name of the clock with the error, click Report Timing, and click OK.
Report Timing will appear.
Documentation: 2.5.2. Report Timing
This error is a DATA2_IN (input port)->din2_reg (first stage FF) error between the different clocks of CLOCK_IN (100MHz) driving the transmitter device and c1 (150MHz) at the PLL output, and since the data rate of the transmitter device is very slow at 50Mbps Since the data rate of the transmitting device is very slow (less than 50Mbps), it is assumed that the system specification allows latching after the 1st edge.
In the next step, we will show how to add multi-cycle SDCs between clocks and analyze them without recompiling.
6. iterating timing constraint changes
This section introduces a feature that is useful when you change a timing constraint and want to immediately see how the change is reflected without having to recompile.
To change the SDC, right-click on the error location, click Set Multicycle (Between clocks), enter 2 for Value, copy the SDC Command, and close with Cancel.
Add the copied SDC to the user SDC (SDC1.sdc), copy and edit the SDC, add the -hold SDC, and overwrite and save.
The "*" (asterisk) in the file name tab will disappear.
Return to the Timing Analyzer and copy the Report Timing command that appears in the Console pane.
In the Tasks pane, click Reset Design, the Read SDC and Update Timing Netlist will change from green to black, and the green check mark will disappear. Now the latest SDC is reflected in the Timing Netlist since the last compilation.
Documentation: 2.3.4. Iteratively Modifying Constraints
Paste the copied Report Timing command into the Console pane and return to display the same Report Timing that was analyzed with the SDC before editing, and confirm that the edited SDC correctly indicates the user specification.
This time, since we added the Multicycle constraint, we can confirm that the constraint that the latch edge is relaxed by one clock cycle is reflected as per the specification.
Point: After recompiling, you will be able to see the results of logic synthesis and place-and-route with the new constraints taken into account.
Conclusion
Timing Analyzer can check various reports.
Please check the reports other than the ones introduced here!
Recommended Articles/Documents
- List of timing-related articles
- Using the Quartus® Prime Timing Analyzer
- Agilex™ 3 FPGA Application Design Guided Journey
Attachments
This is an archive of the sample projects used in this article.
Quartus Pime Pro Edition v25.1
Reference: Easy Environment Reproduction with Archive Files
For a list of the "Tried it with Agilex™ 3" series Click here