Introduction
FPGA (Field Programmable Gate Array) is a programmable digital LSI device. HDL (Hardware Description Language) is the standard method.
One method is to actually run the program on a board equipped with an FPGA (e.g., development kit) to check if the HDL is correctly expressing the desired behavior, but in situations where this is not possible, simulation is used to check and analyze the behavior.
If it does not work as desired, debugging is the process of clarifying the differences and modifying the HDL.
In this article, we will show you how to create a simple HDL description on Quartus Prime Pro (version 25.1) for Agilex 3 and check it in Simulation.
Simulation is performed using Quartus Prime Pro and Questa Questa altera FPGA Edition, which is bundled with Quartus Prime Pro, is used for Simulation, which is invoked from Quartus.
(Some versions may be Questa Intel FPGA Edition, but please consider it the same way.)
You can download the project archive file test_design_Agilex3sim_25_1.qar from the bottom of the page. Extract it with Quartus Prime Pro Edition version 25.1 to start from "3. Run Simulation".
Note: Although this article uses Agilex 3 as an example, the procedure is the same for all other device families supported by Quartus Prime Pro Edition, including the Agilex family and Stratix 10. The procedure is also supported by recent versions of Quartus Prime Standard Edition.
Point: In addition to Questa altera FPGA Edition, the tools listed in 1.7 Supported Simulators in the Quartus Prime Pro User Guide are also supported as Simulation Tools.
1. build HDL design for simulation on Quartus Project
First, start Quartus Prime Pro Edition and build an HDL design for simulation on Agilex 3 Project.
After launching the Quartus software, use the New Project Wizard to create a project targeting the Agilex 3 device, and configure the Simulation Tool settings available in the Wizard.
(Creating a project step 1: Start New Project Wizard)
In New Project Wizard, first set the working directory and project name (test_design in this article).
(Create project step 2: Set working directory and project name)
Next, select Agilex 3 as the target device.
(Create project step 3: Select Device)
Specify Questa intel FPGA Edition as the Simulation tool and Verilog as the HDL language.
(Create project step 4: Specify Simulation tool)
Create the HDL file you want to simulate. This time, use the template Binary Counter provided in the text editor as is.
( Create HDL file step1: File -> New to start creating a new design-related file)
( Create HDL file step2: Specify Verilog HDL )
A text editor for Verilog HDL will be launched. Detach and resize the window as necessary to make it a comfortable size for your work.
(Creating the HDL file step3: Startup screen of the text editor)
Right-click on the editor and select Insert Template from the pull-down menu that appears.
( Create HDL file step4: Run Insert Template )
The Insert Template window will open. Select Verilog HDL Binary Counter from the left menu, insert the contents with Insert, and close the window.
(Create HDL file step 5: Insert Verilog HDL Binary Counter)
Change the module name from binary_counter to "test_design", the same as the project name, and save the file as "test_design.v Save as "test_design.v" under File -> Save As in the editor.
Check the "Add file to current project" checkbox and save the file. The HDL file you want to simulate is now complete and registered in the Quartus Project.
Point: You may now run Analysis & Synthiesis or Compile to check the HDL you have created. You can estimate the resources used by the design and check for errors and debug errors.
2. Creating a Test Bench
Next, create a testbench for Simulation.
In a text editor, generate a Verilog file in the same way as the HDL above, and copy and paste the following text for the contents.
`timescale 1ns/1ns
module tb_test_design;
parameter WIDTH=64;
reg clk;
reg enable;
reg reset;
wire [WIDTH-1:0] result; // count;
parameter HCK = 5; // 100MHz TCK=10ns
initial begin
reset = 1'b1;
enable = 1'b1;
#(HCK*7) reset = 1'b0;
#(HCK * 2 * 100000000) $stop;
end
initial begin
clk = 1'b1;
forever #(HCK) clk = ~clk;
end
test_design #(WIDTH) DUT
(
.clk(clk),.
.enable(enable),
.reset(reset),
.count(result) //,.
);
endmoduleSave this as a testbench file named "tb_test_design.v"
Now you have the necessary HDL files for Simulation.
The contents of the testbench are described below.
The first line is the timescale for Simulation.
The third line is the module name of the top module in the design HDL with "tb_" appended with the intention of representing the testbench.
The fourth line is a list of parameter to override, and lines 5-8 are declarations of signals for input and output.
To parameterize the clock period, the half cycle HCK is declared as a parameter in line 10. Assuming a clock frequency of 100 MHz, the period TCK = 10 ns, so HCK = TCK/2 = 5 ns.
The initial statement on lines 12-17 describes the behavior of the reset and enable signals and the Simulation termination operation. The enable signal is fixed high.
Simulation is terminated by using $stop to specify "stop".
stops after "1 second" of clock cycles at 100MHz.
The clock signal clk is represented by the initial statement in lines 19-22.
Time #0 starts high as the rising edge, and the forever statement on line 21 inverts the signal every half cycle.
The top "test_design" of the design is instantiated with the instance name "DUT" (meaning "Design Under Test").
The output pin count is received by the wire signal "result".
The contents of the testbench are as shown above, so endmodule is placed at the end, as shown in line 32.
Reference material: Let's try it for the first time! Testbench ~Verilog-HDL Edition
3. Run Simulation
Run Simulation according to the contents of the following reference materials
-Reference Material How to easily perform RTL simulation with the Run Simulation feature of Quartus® Prime Pro Edition
Skip the steps that have already been performed and that are not needed ("Register Design in Project" and "Generate Simulation Model for IP").
Setup and check the path settings in order starting with "EDA Tool Path Settings".
In "Specify Simulator / Language", specify Verilog HDL.
Open Assignments → Settings → EDA Tool Settings from the menu.
[Click "New" to "Register Test Bench".
Test bench name is set to the module name "tb_test_design" of the test bench you created, Simulation period is set to Simulation period is controlled by $stop statement in the testbench, so select "Run simulation ....". For File name, use the browse button [...] or type "tb_test_design". or enter the file name directly and register "tb_test_design.v" by clicking [Add].
After completing the "Simulation Flow Settings," click [Apply][OK] to complete the settings and close the Settings window.
Start and run Simulation as described in "How to Operate".
Run "Analyze & Elaboration".
You will be warned with a Critical Warning to use "Reset Release IP," but ignore it this time and proceed.
(We recommend using it in the actual design.)
View menu > Launch the Tcl Console window and enter and execute the following commands.
execute_flow -simulation
Since there may be a mistake in the HDL description and the simulation may stop with an error, click on the Questa icon to open the main window and check if any errors are displayed in the Transcript window.
Especially, since the testbench is checked by the Tool for the first time in Simulation, it is often the cause of errors at this time. There are many factors that can cause errors. Grammatical errors include signal name mismatches in typos, typos in commas and colons, and variables that are not of the correct type. It can also be a problem with installation or licensing.
For example, the following error occurs when a user forgets to type a semicolon ";" at the end of a line.
Read the error message for the location and clue, check the HDL, and make the correction. Note that Quartus will not respond until you exit Questa and click "Flow was successful" [OK], as described in the "Additional Notes" section of the Reference Material.
(If you have corrected the error, run the Simulstion command again from the Quartus Tcl console.)
If there are no problems with the HDL, including the testbench, simulation will continue until the $stop described and then stop.
Since this design is relatively small in scale, it is expected to stop in a few minutes.
4. Checking the waveforms
After running the simulation, if the wave window is set to display waveforms, the wave window will open and the resulting waveforms will be obtained. The method in Section 3 is also set to display the waveform in the wave window. In this section, we will introduce simple operations to check and analyze waveforms in the wave window.
The Toolbar is displayed between the menu bar and the waveforms in the Wave window.
Right-click in the Toolbar area and check On/Off in the pull-down menu to show/hide them.
For example, if only Mode, Wave Cursor, and Zoom are displayed, the waveform will be simplified as shown below.
The horizontal direction is the time axis, so you can repeat zooming in and out to visually check the waveform to track, confirm, and analyze the overall flow, find a specific pattern, and track the relationship between delays and values among signals in detail.
Commonly used zooming operations include the following
・Zoom Full : Screen Fit display of the entire simulation time
・Zoom In (2x) : 2x zoom in
・Zoom Out (2x) : 2x zoom out
・Zoom Area : Drag & Drop to zoom in on a specified area
- In Zoom Mode, left-click to view the left/right range and Drag & Drop downward (bottom left or bottom right) (Zoom Full for top left direction, Zoom Out for top right direction)
The cursor can be used to accurately read the time relationship between signal events. In the default setting, a single cursor is displayed in the Wave window at time 0.
While a single cursor can be used to read the time of an event, such as the edge of a signal, the two states are often used to add another cursor in order to read the relationship between two events.
To add a cursor, click the Insert Cursor icon in the Wave Cursor Toolbar, or click the Insert Cursor icon on the left end of the time display line below the signal name. (The icon is a "+" as shown in the figure, but the design of the icon is different.)
To delete an unneeded cursor, select (highlight) the cursor and click the Delete Cursor icon in the Wave Cursor Toolbar, or click the Remove this cursor icon at the left end of the cursor line. (Similarly, they are each a "-").
The ability to perfectly align the cursor with an event (value change) allows for accurate time readings and confirmation that an event has occurred/not occurred.
Select (highlight) the signal and cursor one at a time and click on the (1) Find Previous Transition or (2) Find Next Transition icons in the Wave Cursor Toolbar. The former moves the cursor to the nearest event time before the cursor, the latter to the nearest event after the cursor.
(It will not move if there is no event until time 0 or the last time.)
These four icons to the right are further limited to those that meet the rising/falling conditions.
If there are more than two cursors, the time difference between the closest cursors will be displayed.
Combined with time alignment to events, this allows accurate readings of clock periods and latency between signals.
Multi-bit bus signals display their values as hexadecimal numbers by default.
You can set the radix to a number that is easier to understand for your system's functionality.
Place the cursor over the signal name or the value to the right of it, right-click, and select the radix you wish to specify from Radix. Commonly used radixes are Binary (binary), Decimal (signed decimal), Unsigned (unsigned decimal), and Hexadecimal (hexadecimal). Floating point numbers can also be recognized if the format is suitable.
If you right-click on the signal name or the value to the right of it and select Format -> Analog(Automatic), the signal value is displayed as a numerical value in a graph.
In the case of Automatic, the scaling of the vertical axis is automatically calculated so that the maximum and minimum values fit into the vertical display range. The scaling of the vertical axis in the case of Automatic is automatically calculated so that the maximum and minimum values fit into the vertical display range.
This confirms that the circuit is performing a monotonically increasing counting operation.
Note that if the number of bits in the signal or the simulation time is relatively large, the display may take some time.
You can copy and paste signals and display them side by side in the Wave window.
This is useful when you want to compare many signals side by side, or when you want to have a graph (Analog) and a value (Literal) side by side for better understanding of the contents.
(To return the Analog display to the value display, right-click on the signal -> Format -> Literal.)
In the figure below, two copies of the signal result are placed vertically, with the top displayed as a graph (Analog) and the bottom displayed as a value (Literal). In the horizontal direction, an enlarged image near time 0, the entire Simulation time display, and an enlarged image near time 1 second are aligned with the signal position.
(In this case, the images obtained from the display are pasted together. (In this case, the images are pasted together from the display. If you create multiple Wave windows, you can compare signals with different magnifications side by side in the tool).
(Lock Cursor)
You can confirm with the cursor that the count from 0 to 99,999,999 → 100,000,000 is done correctly in 1 second, including the count result (displayed in Literal). (By modifying the HDL to return from 99,999,999 to 0, you can create a counter that repeats the same action every second and use it for applications such as clocks.
Note that moving the cursor during operation can be prevented with the lock button (Lock Cursor) on the left end.
Sliding the scrollbar is the most intuitive way to move the display position, but you can also use the following method to jump around the display while it is zoomed in.
Right-click on the following time stamp to directly enter the time and move.
Conclusion
With Quartus Prime Pro and the corresponding Questa altera FPGA Edition installed, we can now prepare a testbench for RTL functional simulation of HDL-designed designs targeting Agilex 3. The Agilex 3 is a very intuitive and easy to use design.
This allows for verification and debugging of the RTL HDL design while intuitively checking waveforms.
We hope you will challenge more advanced RTL HDL design by making full use of various functions of Simens Questa Simulation Tool that we have not been able to introduce here.
For a list of the "Tried it with Agilex™ 3" series Click here
Attachments