Introduction
When it comes to debugging FPGAs, the first thing that comes to mind is SignalTap Logic Analyzer is what most people think of when they think of debugging FPGAs.
SignalTap Logic Analyzer is a powerful tool that allows you to "observe" internal signals in real time. However, in FPGA development, there are many situations where you want to not only "observe" but also check the operation by giving arbitrary signals.
This is where In-System Sources and Probes (ISSP) comes in: ISSP is a tool that allows you to inject signals into the FPGA using JTAG, or to give control signals to the FPGA, and it supports debugging with a different approach than SignalTap.
In this article, we will introduce the basic usage of ISSP, how to set it up, and how to check its operation by applying signals to an Agilex™ 3 FPGA.
1. environment setup
Download the zip file from the bottom of this page and extract it to any location on your PC.
The environment we used for this project is as follows.
Tool: Quartus® Prime Pro Edition V25.1.1
Development kit used: Terasic , Inc: Atum A3 Nano
After extracting the zip file, open Quartus and select File => Open Project => golden_top.qpf from the menu. This will open the project.
When the project is ready, press the compile button with the blue triangle. This completes the validation preparation.
During compilation, the design will be explained below.
2. Explanation of the design
The design consists of a simple counter as shown below.
The last module called is ISSP, and ISSP is embedded in the design as shown above.
A block diagram is also shown below.
In this case, the 4-bit counter can be controlled from either a button on the board or the ISSP, and the result can be checked from the ISSP and the LED on the board.
The design we have prepared this time already includes the ISSP IP, but when actually used, it is called from the IP Catalog as shown below.
The number of ports required for debugging can be selected from the Probe Port (to check signals) and Source Port (to drive inputs to the user design) items as shown below.
In this case, the design is created with Probe Port set to "4" to check the output of a 4-bit counter and Source Port set to "2" for the reset and count-up input signals.
3. operation of In-System Sources and Probes
After compilation, connect Terasic's Agilex™ 3 evaluation board, "Atum A3 Nano", to the PC with a USB cable and turn on the board.
Select the In-System Sources and Probes Editor in the Tools section of the Quartus menu.
Select "Atum A3 Nano" in the Hardware section, select golden_top.sof generated by compilation as the file to be written, and press the Program Device button.
(golden_top.sof is generated in the output_files folder)
You are now ready to go. First, let's check if the board is working; you can see that each time you press the KEY0 button, the LED counts up by 1 bit. 16 presses will return the LEDs to their original state (all lights off).
Next, let's start from ISSP. To make it easier to control each signal, press the button marked with a plus sign to change from bus notation to 1-bit notation.
With all LEDs off, click on the Data portion of issp_source[0] to change the value from 0 to 1.
(Since data is exchanged via JTAG communication, it may take several seconds to reflect the change depending on the environment.)
The LED on the board will light up as if you had just pressed the KEY0 button. Since "1" means that the button is being held down, click on the Data section again to change the value from 1 to 0.
Repeat this process to count up the LEDs by 1-bit increments as before. This is the "Source" function.
Next, let's look at the "Probe" function. Press the Read Probe Data button while the LED is lit.
You can see that the Probe Data and the LEDs are correlated.
Change the LED pattern and press the Read Probe Data button again to update the waveform.
In this way, the ISSP function can be used to virtually reproduce external inputs and outputs and check their operation even if there are no signal inputs or points to probe on the board.
4. Conclusion
ISSP can handle up to 512-bit signals for both the "Source" and "Probe" functions, allowing debugging of even complex designs.
Even in cases where signal I/O is not available on the board, debugging can be performed by external control, dramatically improving the accuracy of design verification and development efficiency. We hope you will find it useful in your daily design work.
Recommended articles/materials
- Debugging Your Design with In-System Sources and Probes
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Altera FPGA Development Flow / FPGA Top Page
For a list of "What we did with Agilex™ 3" series Click here