Introduction
This article describes the Agilex™ 3 Evaluation Board Atum and the Hyper Register by implementing the FPGA Fmax, the operating frequency of Fmax by implementing the Hyper Register. Agilex™ 3 Hyper-Pipelining feature of Agilex™ 3 by enabling the Hyper-Pipelining feature of Agilex™ 3, ALM between the registers. Hyper Register between ALM registers, eliminating long routing delays and reducing F max in the overall design by eliminating long routing delays. Hyper Register Fmax improvement by implementing the Hyper Register This section describes how Fmax can be improved by implementing Hyper Register based on a sample design.
Sample design (file name: "top_Hyper_Register.qar) can be downloaded from the bottom of this page.
1. What is Hyper Register What is
Hyperflex The core architecture uses the traditional FPGA Unlike traditional FPGAs, the Hyperflex core architecture adds millions of registers at the intersections of the wires between ALMs. To distinguish these registers from those located within logical blocks, the Hyper Register to distinguish them from the registers located in the logical blocks. The following figure shows the Hyper Register located in the interconnections between ALMs.
One technique to improve Fmax is to insert pipeline registers. In the conventional design method, it is necessary for designers to insert the necessary number of pipeline registers at each stage of a multi-stage combinational circuit by themselves. On the other hand, with Agilex™ 3,which supports the Hyperflex core architecture, the designer only needs to insert the required number of pipeline registers before and after a circuit with multiple stages of combinational circuitry, and Quartus Prime's retiming function is enabled, automatically placing the registers in the critical path . The Quartus Prime retiming function automatically places the registers in the critical path and Hyper Registers as needed. This reduces the designer's man-hours and improves Fmax.
2. environment setup
The design of "top_Hyper_Register.qar" is created with the following tool version
・ Target device : Agilex™ 3 (A3CZ135BB18AE7S)
・ Tool version : Quartus Prime Pro Edition ver. 25.1.1
First, download "top_Hyper_Register.qar" from the bottom of the page and select Project > Restore Archived Project.
Specify the path where you saved "top_Hyper_Register.qar" in the Archive name: field, specify the destination path in the Destination folder: field, and select OK. project by specifying the path where you saved the "Quartus Prime" project in the "Archive name:" field.
Once the project has been extracted, click on the Compile button in the blue triangle (see below) to compile the project.
You are now ready to check the implementation of Hyper Register and the Fmax values.
3. explanation of the design
The design provided as a sample is a design that implements an integer divider. Since the divider is implemented as a combinational circuit, the datapath delay (the time it takes for a signal to arrive from the input to the output) is likely to be large. As a result, the critical path delay, which is the longest path delay of the entire design, becomes large, which can easily cause Fmax to drop.
Therefore, this time, we have decided to use the Fmax is likely to be lowered, we have used a divider design that is prone to Fmax reduction, Hyper Register Fmax improvement by Fmax improvement by Hyper Register can be confirmed. The Hyper Register is also used in the design of the divider. In addition, the Fmax to insert pipeline registers before and after the division circuit, where Fmax hyperpipe_vlat module is implemented . With this, Quartus Prime implements the Hyper Register and implements the Hyper-Retiming functionality, Hyper-Retiming Function Quartus Prime then considers the optimal number of stages and placement locations and automatically allocates them to improve Fmax.
In this design, the maximum number of pipeline stages that can be added is set to MAX_PIPE parameter.
*The design actually shows how the Fmax value changes and how the Hyper Register is implemented by changing the value of MAX_PIPE.
4. implementation method
The module of the virtual register to allow pipelining, the hyperpipe_vlat which is a module of virtual register to allow pipelining, is provided in Quartus Prime, so this module is implemented before and after the circuit where the delay tends to be large.
The clock of the hyper register must be allocated to the global clock, so if the corresponding clock is not allocated to the global clock, set the global clock.
Please refer to the handbook for other guidelines regarding the insertion of pipeline registers.
Hyperflex® Architecture High-Performance Design Handbook -2.3.2.2 Automatic Pipeline Insertion
5. Check the implementation of Hyper Register
Implemented in the template Virtual register to allow pipeline is shown in the following RTL module in blue in the RTL design below, HDL The results reflect the description of the HDL design as is. RTL Analyzer RTL Analyzer
RTL information can be viewed in schematic format by selecting Tools > Netlist Viewer > RTL Analyzer in Quartus Prime.
The Technology Map Viewer (Post-Fitting) allows you to seehow the Fmaxhas been improved by eliminating critical paths throughthe implementation ofHyper Registers inappropriate locations throughout the circuit (Hyper-Retiming). An overall view of the circuit is shown below.
In Quartus Prime, go to Tools > Netlist Viewer >> Netlist Viewer >> Netlist Viewer >> Netlist Viewer >> Netlist Viewer Technology Map Viewer (Post-Fitting) in Quartus Prime to view RTL information in schematic format.
The following is an enlarged view of a part of the circuit in the Technology Map Viewer (Post-Fitting).
Hyper Register The implementation of the Hyper Register is shown in the following figure. Technology Map Viewer (Post-Fitting) on the HYPER on the Technology Map Viewer (Post-Fitting).
The number of implementations of Hyper Register The number of implementations of Compilation Report on the Compilation Report. Fitter > Place Stage > Resource Usage Summary on the Compilation Report.
Fmax can be found in the Compilation Report on the Fitter > Fast Forward Timing Closure Recommendations > Clock Fmax Summary on the Compilation Report.
6. If Hyper Register is not implemented
If the hyper register is not implementeddespite the use of the hyperpipe_vlattemplate in the user design, the Fast Forward Timing Closure Recommendations report should be followed.
To output the report, check the Fast Forward Timing Closure Recommendations blank box in theCompilation Dashboard .
The report can be viewed by going toFitter > Fast Forward Timing Closure Recommendations > Fast Forward Details for Clock Domain xxx onthe Compilation Report .
By modifying the design in accordance with the contents of this report, Hyper Register will be used and Fmax will be improved. Please refer to the User Guide for more information on the report.
Hyperflex® Architecture High-Performance Design Handbook -4.1.1. Step 1: Compile the Base Design
7. MAX_PIPE in this design is as follows MAX_PIPE value of MAX_PIPE in this design
MAX_PIPE parameter in this design, the Hyper Register is implemented in the optimal path for the design. Hyper Register is implemented and MAX_PIPE=15 MAX_PIPE=15 MAX_PIPE=15 Fmax values saturate after MAX_PIPE=15. The graph below shows that Fmax improves overall.
In addition, depending on the design improvement depends on the design. Fmax varies depending on the design.
8. summary
By implementing Agilex™ 3 Hyper Register, the Fmax of the entire design can be improved by eliminating the long wiring delay that has been an issue up to now. Please refer toAltera Hyperflex Architecture Handbook fordetails.
Hyperflex® Architecture High-Performance Design Handbook
https://www.intel.com/content/www/us/en/docs/programmable/683353/25-1-1/faq.html
AN 917: Reset Design Techniques for Hyperflex® Architecture FPGAs
Also, Hyper Register Fmax Fmax The design used to validate the Fmax of Hyper Register is attached, Hyper Register Please use it as a sample when implementing the Hyper Register. MAX_PIPE value, you can change the Fmax and Hyper Register by changing the MAX_PIPE value.
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