Altera FPGAs do not provide transceiver eye masks.
Eye masks are defined by each protocol standard, such as PCI Express or Ethernet, and are typically provided by oscilloscopes or compliance test software.
FPGA vendor tools are not intended for standard compliance testing and instead employ mechanisms to evaluate link quality based on BER.
During the design phase, it is recommended to simulate the pre-CDR waveform after the CTLE/VGA/DFE equalizers using transmission line S-parameters or IBIS-AMI models to verify the eye opening and jitter.
For link bring-up and tuning purposes, tools like the Transceiver Toolkit can be used to optimize parameters from a BER perspective.
Please note that the eye diagram visible in the Transceiver Toolkit visually represents the bit error rate (BER) using color. This differs from the mechanism used for pass/fail determination based on the absolute voltage and time axis defined by the standard.