Introduction.
What are the SDC settings and analysis results for a system with data and inverted clock input, such as Source Synchronous' center-aligned input?
This article presents SDC and analysis results using a simple system as an example.
System Configuration and I/F Specifications
Let us consider an example with the system configuration and I/F specifications as shown in the figure below.
SDC Constraints
In this article, we will try to set up a configuration using a virtual clock for analysis that is synchronized with the actual clock input and data.
CLK and VCLK are configured with the clock image in Figure 2.
create_clock -name CLK -period 10.000 -waveform {5.000 10.000} [get_ports {CLK}]]
create_clock -name VCLK -period 10.000 -waveform {0.000 5.000}
Then, VCLK is set to -clock in set_input_delay, and the phase difference between VCLK and DATA is calculated and set to Value.
The set Value is the image of max/min in Figure 2.
set_input_delay -clock {VCLK} -max 1.000 [get_ports {DATA}]]
set_input_delay -clock {VCLK} -min -1.000 [get_ports {DATA}]]
Board delay is not taken into account.
Report Timing
Create a Netlist for timing analysis in Timing Analyzer.
Open the Report Timing Setup screen, set Report conditions, etc., and click Report Timing.
In Setup analysis of Report Timing, you can analyze the result set by -max of set_input_delay.
In the Hold analysis of Report Timing, you can analyze the result set by -min of set_input_delay.
This completes the SDC example and analysis for Source Synchronous Input.
Please take a look at them for reference.