Introduction
Synopsys Design Constraints (SDC) files are used to place constraints on FPGA designs.
SDC files are the standard format for timing constraints in LSI designs and have been adopted by the FPGA industry.
When registering SDC files in Quartus® Prime development software (hereafter referred to as Quartus® Prime), one must be careful about the order of configuration when multiple SDC files exist. In particular, if IPs are used in the design, an SDC file will be created for each IP in addition to the user-created SDC file.
How to set up SDC files in Quartus® Prime
(1) Open Project...
Select File menu -> Open Project. Select File menu -> Open Project....
(2) Open the SDC file settings screen.
Select Assignments menu -> Settings.... Select "Settings..." and select "Timing Analyzer" from "Category:".
(3) Select "Timing Analyzer" from "Category:".
The registered SDC files are displayed.
If no SDC file is displayed, add an SDC file.
If IP is incorporated in the design, make sure the qip file is registered.
(The SDC file is registered in the qip file.)
Order of SDC file registration in Quartus® Prime
The SDC file registered at the bottom has the highest priority.
If the same constraint is registered in multiple SDC files, the description in the SDC file registered at the bottom has priority.
When using IP or other devices, the SDC file created by the user must be registered at the bottom of the SDC file. In particular, when using a DDR controller, be aware that timing analysis may not be performed correctly if the user-created SDC file is not registered at the bottom of the SDC file.