Introduction
The memory controller of the Intel® Arria® 10 FPGA is a hard memory controller, one for each I/O Bank, allowing multiple memory controllers to be installed in the same I/O Column. On the other hand, there is one calibration module for each I/O Column, so if multiple memory controllers are installed, calibration is performed sequentially, not simultaneously.
This article explains how the calibration works.
How are Intel® Arria® 10 FPGA memory controllers configured in a device?
The Intel® Arria® 10 FPGA device has two I/O Columns with one hard memory controller implemented in each I/O Bank, as shown in the figure below.
There are multiple I/O Banks on an I/O Column, and one I/O AUX containing Nios® ll that performs calibration is implemented on
one I/O Column.
How Memory Controller Calibration Works
Since there is only one I/O AUX with Nios® ll for calibration per I/O Column, if there are multiple memory controllers in an I/O Column, they are calibrated one after the other.
Therefore, if you have a system with multiple memory controllers, please note that it may take some time until all memory controllers are calibrated.
Calibration Completion Time
The time required for a single memory controller to complete calibration depends on the configuration of the memory.
For example, for DDR3, x64 UDIMM, DQS x8, DM on, 1 rank, 933 MHz, the average calibration time is "102 ms".
For detailed calibration times, please refer to the following documents
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https://www.intel.com/content/www/us/en/programmable/documentation/hco1416493470528.html#mhi1461170950981
= > Table 58. Arria 10 EMIF IP Approximate Calibration Times
Reference