Description.
There are several rules for pin placement on the Altera® FPGA 10 series EMIFs, and failure to properly place the pins will result in Fitter errors.
This page is intended to help you understand the Altera® FPGA 10 series EMIF pinout rules and how to efficiently place pins.
(Here, Altera® FPGA 10 series means Stratix® 10 FPGA, Arria® 10 FPGA, and Cyclone® 10 GX FPGA)
Overview
The following are the main points to be considered when pin-locating EMIFs.
I/O columns, I/O banks, and I/O lanes
Address command pins
Data pins
Understanding the above placement rules will help you efficiently place the pins in the desired locations.
Configuration of I/O Banks
The configuration of I/O columns and I/O banks is as follows.
Each I/O column consists of multiple I/O banks.
Up to one memory IP can be implemented in each I/O bank.
Each I/O bank consists of four I/O lanes.
Each I/O lane consists of 12 I/O pins.
Each I/O bank consists of 12 I/O pins. 1 I/O bank (48 pins) = 1 I/O lane (12 pins) × 4.
Using the figure below as an example, I/O bank 3F consists of I/O lanes 0~3.
The configuration and number of I/O banks varies depending on the device.
There are two types of I/O banks, LVDS I/O and 3V I/O. The 3V I/O bank has the following limitations.
Frequency limitation: Up to 533 MHz
OCT cannot be used (disabling OCT is not recommended)
Memory IP placement in the 3V I/O bank is deprecated.
In the figure above, the yellow bank is the 3V I/O bank, and memory IP placement in this I/O bank is deprecated.
About Address Command Pins
The address command pins have a fixed position in the I/O bank, although the I/O bank in which they are mounted can be selected.
Three lanes (Index numbers 0 to 35) or four lanes (Index numbers 0 to 47) are used for address command pins alone.
The table below shows the External Memory Interface Pin Information file.
- (Index numbers 0 to 47 are assigned to the address command pins.
- The number of lanes to be used can be confirmed by referring to this document and the memory configuration.
The files for each device family are as follows
- Stratix® 10 FPGA : https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/dp/stratix-10/stratix10emif.pdf
- Arria® 10 FPGA : https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/dp/arria-10/arria10emif.xls
- Cyclone® 10 GX FPGA : https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/dp/cyclone-10/cyclone10gxemif.pdf
The table below is the Device Pin-Out File.
URL: https://www.altera.com/design/devices/resources/pinouts
- Each I/O bank is also assigned an Index number from 0 to 47.
Based on the above information, it is necessary to place pins so that the Index number of each bank and the Index number of the address command are the same.
About Data Pins
Data pins are not fixed, but there are some rules.
A DQ/DQS group should be placed in one I/O lane (8 bits per lane, up to 32 bits per bank).
Pins can be interchanged within a DQ/DQS group or per DQ/DQS group.
Data pins are placed in the I/O bank in which address command pins are placed or in adjacent I/O banks.
Address command pins and data pins can be placed in the same I/O bank.
Address command pins and data pins cannot share the same I/O lane.
When using multiple banks
Depending on the configuration of address command pins and data pins, there are cases where EMIF can be placed in a single I/O bank and cases where multiple I/O banks are required.
Cases in which EMIF can be placed in a single I/O bank
- When 3 lanes are used for address command pins + 8-bit data width
Cases in which multiple I/O banks are required for EMIF placement
- When 4 lanes are used for address command pins
- When 3 lanes are used for address command pins + Data width is 16 bits or more
When multiple I/O banks are required for a single memory IP, the following rules apply.
The I/O banks must be located adjacent to each other in the same column.
Data pins should be centered on the I/O bank where the address command pins are located.
When mounting multiple EMIFs
If the following conditions are met, the data pins of different EMIFs can be shared in the same I/O bank.
Same memory protocol
Same operating frequency
Same I/O Standard
Same supply voltage
For example, in the case of a DDR3 (16 bit data width) x 2 interface as shown in the figure below,
For example, in the case of a DDR3 (data width 16 bits) × 2 interface as shown in the figure below, it is possible to reduce the number of I/O banks consumed to 3 by sharing I/O lanes.
(Without I/O lane sharing, four I/O banks are consumed.)
Unused pins can be used as GPIOs.
How to Perform Efficient Pin Assignment
There are two ways to perform efficient pin placement
(1) Compile with Fitter Free
- If you do not have a desired pin assignment location, the most reliable and easy way is to compile with Fitter Free.
- Compiling with Fitter Free will automatically place pins in the appropriate locations.
- (1) : Automatic placement of pins to satisfy the constraints, but if there is no combination that satisfies the constraints, a Fitter error occurs.
(2) : Compile by specifying only one address command pin to a specific bank
- This method is effective when you want to place EMIFs in the desired I/O bank.
- If only one address command pin is specified, pins are automatically placed based on the specified position.
- For example, when 72-bit memory IP is to be implemented in the 3A to 3C I/O banks in the following device, simply specify one of the address command pins as 3B and compile, and the pins will be automatically placed in the 3A to 3C I/O banks.