Introduction
The Quartus®Prime development software can generate an example design for the EMIF core.
This design performs a write/read test of a specified size on the RTL to external memory, determines Pass/Fail, and stops.
However, by changing the RTL description, it is possible to operate continuously without stopping.
This article introduces the setting method.
In the case of continuous operation, "Pass" status will disappear and only "Fail" judgment will be made.
The following environment is used in this article.
- FPGA: Arria10 family
- Language: Verilog
- Quartus®Prime Development Software Pro/Standard Edition: Version 18.1
How to Generate Example Designs
The settings for the generated Example Designs are made on the Example Designs tab of the EMIF Core Configuration screen, including whether or not Synthesis and Simulation are generated and the language in which they are generated.
After setting, click "Generate Example Designs..." in the upper right corner. in the upper right corner.
This will open the "Select Example Design Directory" screen, where you can set the locations and folder names to be generated, and click OK.
This will start the Example Design generation.
The folders to be generated differ between the Pro and Standard editions.
The figure below shows the result of generating a folder named "emif_0_ed".
In the Pro Edition, a folder named "ip" is generated.
The block structure of the generated design is shown in the figure below.
The Example Design for Synthesis includes the EMIF core and a module called Traffic Generator.
The Example Design for Simulation includes Traffic Generator, Memory Model, and Status Checker in addition to the EMIF core.
How to change RTL description
To run Example Design continuously, change the RTL description of Traffic Generator.
The files to be changed and the folder to save them are different between Pro Edition and Standard Edition.
Pro Edition
File to be changed
- Synthesis : ed_synth_tg.v
- Simulation : ed_sim_tg.v
Save folder
Refer to the following figure.
Standard Edition
File to be modified
- Synthesis : ed_synth.v
- Simulation : ed_sim.v
Save folder
Refer to the following figure.
RTL change point
The RTL change point is the part that instances the "altera_emif_avl_tg_top" and change the value of "TEST DURATION".
The following table shows each setting value and the number of iterations.
| Setting | Number of times |
| SHORT | 1 time |
| MEDIUM | 1000 times |
| INFINITE | Continuous operation |
SUMMARY
In this article, we have introduced a concrete procedure for continuous operation of an EMIF-generated Example Design.
Since the behavior of the Example Design can be changed with simple customization, it can be useful to check the behavior of your product in advance.