Introduction
The Arria® V FPGA / Cyclone® V FPGA memory controller supports the ODT (On Die Terminartion) feature and can control the ODT of memory devices.
ODT is controlled by the ODT signal output from the memory controller IP implemented in the FPGA.
On the other hand, when the chip select signal (signal name : mem_cs) is 2-bit, it is necessary to understand how the ODT signal (signal name : mem_odt) asserts for the device memory whose mem_cs is asserted.
This article explains how the two bits of the ODT signal behave when the chip select signal is set to 2 bits in the memory controller IP of the Arria® V FPGA / Cyclone® V FPGA.
Overview of ODT Control
The ODT setting for memory device can be configured in the Arria® V FPGA / Cyclone® V FPGA memory controller IP.
Figure 1 below shows the "Memory Parameters" tab of the memory controller IP. The values set in this tab are written to the memory device mode registers (Mode Register 0/ModeRegister 1/ModeRegister 2 ).
ODT Rtt nominal and Dynamic ODT, which can be controlled by ODT signals, can be selected
in the pull-down box enclosed in red in Figure 1.
Figure 1: Mode register setting screen of UniHY memory controller IP
ODT Rtt nominal and Dynamic ODT have the following meanings.
- ODT Rtt nominal value: ODT setting that is enabled during non-write access to memory
- Dynamic ODT (Rtt_WR) value: ODT setting that is enabled during write access to memory
See also the following documents
-
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/external-memory/emi_plan.pdf#page=84
=> 2.1.2. Dynamic ODT
Even when the ODT signal is 2 bits, the settings for both of these ODT signals are set in common.
Relationship between the chip select signal and the ODT signal
When the chip select signal is 2 bits, the 2 bits of the ODT signal operate as follows.
External Memory Interface Handbook Volume 3: ReferenceMaterial
8. Functional Description-HPC II Controller
8.3.7. ODT Generation Logic section
Table 1: Operation relationship between mem_cs and mem_odt signals
"Write On" and "Read On" in Table 1 mean the following
- "Write On": Bit of the chip select signal (mem_cs) to be written
- "Read On": Bit of the chip select signal (mem_cs) to be read
Table 1 shows that
- When writing, mem_odt[1:0] is Enable for both mem_cs[0] and mem_cs[1] when "Write On" is set to "Enable".
- When reading, the opposite bit of mem_odt becomes Enable for the bit of mem_cs.
The result is as follows.
In actual RTL simulation, we can confirm that the behavior is the same as Table 88 and Table 89 in Table 1 above.
Figure 2: RTL simulation waveforms of mem_cs and mem_odt signals
Relationship between ODT Signal and Rtt_nom / Rtt_WR
There are two types of resistor values that can be set for ODT: Rtt_nom and Rtt_WR, and you can select "do not use ODT" or "set to RZQ/x" (see Figure 1).
The relationship between the chip select signal and the ODT signal is clear from Table 1 and Figure 2, but what is the relationship between Rtt_nom and Rtt_WR?
We now define "active state" and "standby state" according to the state of access to the memory device, as follows.
- Active state: Memory in which the chip select signal is asserted and some access is being made
- Standby state: Memory in which the chip select signal is deasserted but no access is being performed.
At this time, Rtt_nom and Rtt_WR are adopted for the active/standby and Write/Read states as shown in Table 2 below.
|
Rtt_Nom = ON Rtt_WR = ON |
Rtt_Nom = ON Rtt_WR = OFF |
Rtt_Nom = OFF Rtt_WR = ON |
Rtt_Nom = OFF Rtt_WR = OFF |
|
| Active state (Write) | Rtt_WR (1) | Rtt_Nom (2) | Rtt_WR (1) | Disable (3) |
| Active (Read) | Disable (4) | Disable (4) | Disable (4) | Disable (4) |
| Standby state (Write) | Rtt_Nom (5) | Rtt_Nom (5) | Disable (6) | Disable (6) |
| Standby (Read) | Rtt_Nom (5) | Rtt_Nom (5) | Disable (6) | Disable (6) |
Table 2: Relationship between ODT signal and Rtt_nom and Rtt_WR
(* ON = "set to RZQ/x", OFF = "do not use ODT resistor")
Table 2 Explanation:
(1) Write state and Rtt_WR=ON, so RTT_WR is used.
(2) Write state and Rtt_WR=OFF, so RTT_Nom is used.
(3) Active state and Rtt_Nom=OFF, so ODT resistor is not used.
(4) In active state Read, no ODT resistor is used
(5) In standby state, RTT_Nom is adopted
(6) In standby state, but Rtt_Nom=OFF, no ODT resistor is used
Conclusion
This article has explained the relationship between the
chip select signal and the ODT signal in the memory controller IP used in the Arria® V FPGA / Cyclone® V FPGA using Table 1 and Figure 2.
The relationship between the ODT signal and Rtt_nom and Rtt_WR is also explained using Table 2.
Please refer to this table when designing memory controller IP.