Introduction
The memory controller in the Intel® Arria® 10 FPGA supports the ODT (On Die Terminartion) feature
to control the ODT of memory devices.
ODT is controlled by the ODT signal output from the memory controller IP implemented in the FPGA.
On the other hand, when the chip select signal (signal name : mem_cs) is 2-bit, it is necessary to understand how the ODT signal (signal name : mem_odt) asserts for the device memory whose mem_cs is asserted.
This article describes the specific configuration procedures for the flexible ODT control that Intel® Arria® 10 FPGAs have.
Specific configuration procedures for the Chip Select and ODT signals
The behavior of the 2 bits of the ODT signal when the chip select signal is 2 bits can be configured on the memory controller IP screen.
Specific Setting Procedure
The specific procedure is as follows.
Open the Arria 10 External Memory Interface.
" Open the "Mem I/O" tab and follow the steps below to configure the settings.
1) Uncheck "Use Default ODT Assertion Tables"
2) Change the ODT resistance value (RZQ/X)
3) In the ODT Assertion Table during Read Accesses / Write Accesses, Set ODT on/off from pull-down menu
* "Read Target" and "Write Target" become active state memory.
4) Check the result with Derived ODT Matrix for Read Accesses /Write Accesses to see if the intended settings have been made.
Figure 1: Memory Controller IP Settings Screen
After setting up the memory controller IP, compile the memory controller IP with Intel® Quartus® Prime development software.
Summary
In this article, the relationship between the
chip select signal and the ODT signal in the memory controller IP used in the Intel® Arria® 10 FPGA was explained using Figure 1.
Please refer to Figure 1 for designing your memory controller IP.