1. Introduction
This article introduces commands that enable configuration and access to build an FPGA-HPS interface for the Cyclone® V SoC / Arria® V SoC.
In Intel® SoC FPGA devices, the FPGA and the HPS (Hard Processor System) coexist, and the HPS to the FPGA is accessed through a dedicated interface called HPS-to-FPGA or Lightweight HPS-to-FPGA (Figure 1). The interface cannot be simply built; a procedure is required to enable access by specific commands.
Figure 1. AXI Bridges configuration screen
2. Enabling FPGA to HPS interface
To access the FPGA from the HPS, the interface between the two must be enabled.
There are two types of interfaces, HPS-to-FPGA and Lightweight HPS-to-FPGA, and at least one of them must be selected. The HPS-to-FPGA and Lightweight HPS-to-FPGA are summarized below (Table 1).
Table 1. Overview of HPS-to-FPGA and Lightweight HPS-to-FPGA
| Interface | Bit Width | Main Applications |
| HPS-to-FPGA | 32-bit, 64-bit, 128-bit |
Large data transfer |
| Lightweight HPS-to-FPGA | 32-bit |
Register access |
How to configure, In the HPS Parameters → FPGA Interfaces tab → AXI Bridges field in Platform Designer, Set either HPS-to-FPGA interface width or Lightweight HPS-to-FPGA interface width to a value other than unused (Figure 2). Refer to Table 1 for the number of bits that can be set.
Figure 2. AXI Bridges Field Settings
When HPS-to-FPGA/Lightweight HPS-to-FPGA is enabled by the above settings, the AXI Master pin is output to the Arria® V / Cyclone® V Hard Processor System in Platform Designer. Connect the AXI master pin to the peripheral you wish to access and generate it in Platform Designer to complete the interface construction.
The AXI master and Avalon-MM slave can be directly connected by the AXI-Avalon-MM bridge that is automatically inserted by Platform Designer.
3. Bridge opening
After creating the interface between HPS and FPGA as hardware, the bridge must be explicitly opened in the source code. The bridge can be opened by Preloader or U-boot.
3-1. How to Open a Bridge with Preloader
3-1-1. Standard Preloader
The Preloader includes a code to open the bridge if the FPGA side has already been configured by default. The specific description is as follows in reset_manager.c.
File location: uboot-socfpga\arch\arm\cpu\armv7\socfpga\reset_manager.c
00297| if (is_fpgamgr_fpga_ready()) {
00298| DEBUG_MEMORY
00299| /* enable the axi bridges if FPGA programmed */
00300| writel(brgmodrst, &reset_manager_base->brg_mod_reset);
00301|
00302| /* remap the enabled bridge into NIC-301 */
00303| writel(remap_val, SOCFPGA_L3REGS_ADDRESS);
00304| }
In the above code, is_fpgamgr_fpga_ready() determines if the FPGA is configured. If it is configured, the bridge is opened at
writel(brgmodrst, &reset_manager_base->brg_mod_reset);
NOTES:
If the FPGA configuration is not completed at this point, the bridge will not be opened.
If the bridge is not opened by the Preloader, it is necessary to open the bridge by U-boot as described below.
If the U-boot is not used in the boot flow, the bridge can be opened on the user application running after the Preloader, or the Preloader can be customized to open the bridge after waiting for the FPGA configuration to complete.
3-1-2. Customizing the Preloader
If you want to customize the Preloader, simply replace is_fpgamgr_fpga_ready() with poll_fpgamgr_fpga_ready() as described above.
The contents of is_fpgamgr_fpga_ready and poll_fpgamgr_fpga_ready are also listed below for reference.
File location: uboot-socfpga\arch\arm\cpu\armv7\socfpga\fpga_manager.c
00065|/* Check whether FPGA is ready to be accessed */
00066|int is_fpgamgr_fpga_ready(void)
00067|{
00068| /* check for init done signal */
00069| if ( is_fpgamgr_initdone_high() == 0)
00070| return 0;
00071| /* check again to avoid false glitches */
00072| if (is_fpgamgr_initdone_high() == 0)
00073| return 0;
00074| if (fpgamgr_get_mode() ! = FPGAMGRREGS_MODE_USERMODE)
00075| return 0;
00076| return 1;
00077|}
00078|
00079|/* Poll until FPGA is ready to be accessed or timeout occurred */
00080|int poll_fpgamgr_fpga_ready(void)
00081|{
00082| unsigned long i;
00083| DEBUG_MEMORY
00084| /* If FPGA is blank, wait till WD invoke warm reset */
00085| for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
00086| /* check for init done signal */
00087| if (is_fpgamgr_initdone_high() == 0)
00088| continue;
00089| /* check again to avoid false glitches */
00090| if (is_fpgamgr_initdone_high() == 0)
00091| continue;
00092| return 1;
00093| }
00094| DEBUG_ MEMORY
00095| return 0;
00096|}
3-2. How to open a bridge with U-boot
The following commands can be written in the U-Boot script (u-boot.scr) to open a bridge.
run bridge_enable_handoff;
Even if you use this method to open the bridge, the FPGA must be configured in advance.
Reference: The following article explains how to edit the U-Boot script.