Introduction
Starting with the v19.1 Standard Edition (v19.1 Std) / v19.3 Pro Edition (v19.3 Pro) of the SoC FPGA Embedded Development Suite (SoC EDS), the bootloader generation flow has changed.
- As noted in the release notes, the bootloader source tree that was bundled with SoC EDS prior to SoC EDS v18.1 is no longer included.
- Starting with SoC EDS v19.1 Std / v19.3 Pro, users will need to obtain the bootloader source tree from GitHub at. This allows the latest boot loader to be used and easily adaptable to updates.
- The modified bootloader generation flow can be found on the RocketBoards.org page below.
Reference: Building Bootloader for Cyclone V and Arria 10
This article describes how to build U-Boot with the following configuration
| Device | Quartus® Version | U-Boot Branch | Linux Branch |
| Cyclone® V SoC | 22.1 Std | 2022.04 | 5.15.70-lts |
Note:
* The above is the device and tool compatibility table as of March 1, 2023 (content will be updated
with each release).
* Starting with release v22.1 Std, the SoC EDS is no longer required to generate the handoff folder for Cyclone® V SoCs. For more information on how the SoC EDS was changed, see Building Bootloader for Cyclone V and Arria 10 page at for more information on how the SoC EDS was changed.
This article describes the old and new bootloader build flow for the Cyclone® V SoC and Arria® V SoC and provides instructions for building a bootloader on the Cyclone® V SoC.
Note:
This article only shows an example build for the Cyclone® V SoC; building the Arria® V SoC is almost the same procedure, so it is omitted here.
Reference:
The official SoC FPGA U-Boot repository can be found at https://github.com/altera-opensource/u-boot-socfpga.
* Branches labeled "RC" are for internal active development and Customer Early Access without official customer support .
* The latest stable branch (without RC label) is strongly recommended for development and production use outside of Altera® (Intel®) at.
* See doc/README.socfpga for Quartus® and device support .
1. Build Flow for Cyclone® V SoC and Arria® V SoC
For the Cyclone® V SoC and Arria® V SoC, the handoff information produced by the Quartus® compilation is provided in several formats, including C source code, XML, and binary files.
The bsp-editor takes this information and translates it into source code that is used to build the U-Boot.
In older versions of SoC EDS, users could set various U-Boot parameters in the bsp-editor GUI.
For versions of SoC EDS older than v20.1 Std, the bsp-editor could be used. However, v20.1 Std or later introduces a new procedure that does not use the bsp-editor .
1-1. Flow before SoC EDS v18.1
In SoC EDS v18.1 and earlier, the following flow was used to build the U-Boot:
Figure 1. Boot Loader Generation Flow in SoC EDS v18.1 and earlier
- Key user options (boot source, enable ECC scrubbing, watchdog, etc.) were set via the bsp-editor GUI or equivalent command line.
- U-Boot source code was included with SoC EDS.
- The Makefile created by bsp-editor allowed the bootloader to be built with a single 'make' command.
1-2. Flow of SoC EDS v19.1 Std / v19.3 Pro to v20.1
The build flow for SoC EDS v19.1 Std / v19.3 Pro to v20.1 is different as shown below:
Figure 2. SoC EDS v19.1 Std / v19.3 Pro - v20.1 Boot Loader Generation Flow
The main differences are as follows:
- All user options defined in bsp-editor no longer apply. They will still be configurable in bsp-editor, but will have no effect.
- All custom user settings must be done directly in U-Boot (device tree, configuration, and source code).
- The Makefile generated by bsp-editor will not build the U-Boot. Instead, use the Makefile included in the U-Boot source tree to make.
- Binary conversion or conversion to an image file can be done by following the instructions on page of Building Bootloader for Cyclone V and Arria 10 on Rocketboards.org.
- The U-boot source code must be obtained by the user from GitHub.
- A tool called qts_filter (part of U-Boot) must be called to convert the handoff files and the files generated by bsp-editor into the format required by the new U-Boot version.
1-3. Flow for v21.1 Std and later after SoC EDS is discontinued
The boot flow after v21.1 Std is as shown in the figure below.
There are some changes due to the discontinuation of SoC EDS:
Figure 3. Boot Loader Generation Flow in v21.1 Std and later
The main differences are as follows:
- With the discontinuation of SoC EDS, bsp-editor (bsp-create-settings) is no longer included in the flow. Instead, the cv_bsp_generator.py script included in the U-boot source tree is used.
- The change from bsp-editor (bsp-create-settings) to the cv_bsp_generator.py script grabs the sources from the handoff folder, formats them appropriately, and then incorporates the header files into the U-Boot source code.
2. How to execute the build
2-1. Prerequisites
■ The following environment is used in this article (the environment used here is just an example):
-
- Host machine running Linux. In this article we used VirtualBox + Ubuntu 20.04 LTS.
- An internet connection to download tools and clone the U-Boot git tree from GitHub. If you have a firewall or proxy, you will need to allow the system administrator access to the git tree.
- SoC FPGA development kit with the desired device: Cyclone® V SoC / Arria® V SoC
■ If you have a proxy, such as an internal network, you will need to configure the following proxy settings:
On your Linux host machine, open the /etc/apt/apt.conf file using a text editor (such as gedit),
write the proxy settings as shown below, and save it.
$ sudo gedit /etc/apt/apt.conf
Acquire::http::proxy "http://proxy.address:proxy.port";
Acquire::https::proxy "https://proxy.address:proxy.port";
Acquire::ftp::proxy "ftp://proxy.address:proxy.port";
* In the above proxy settings, proxy.address means the proxy address, and proxy.port means the proxy port number.
Please set the appropriate settings according to the user's network environment.
On your Linux host machine, open the .bashrc file in a text editor (such as gedit),
add the following proxy to the last line, and then save the file.
$ gedit ~/.bashrc
export http_proxy="http://proxy.address:proxy.port"
export https_proxy="https://proxy.address:proxy.port"
export ftp_proxy="ftp://proxy.address:proxy.port"
* In the above proxy settings, proxy.address means the proxy address, and proxy.port means the proxy port number.
Please set the appropriate settings according to the user's network environment.
Close the terminal on your Linux host machine and then start it again.
■ Open the terminal and enter the following command to update the package information:
$ sudo apt update
$ sudo apt upgrade
■ If you have a proxy, such as an internal network, it is necessary to configure proxy settings by using the following git config --global command (please configure the appropriate settings for your network environment):
$ git config --global http.proxy http://proxy.address:proxy.port
$ git config --global https.proxy https://proxy.address:proxy.port
■ Download and set up the toolchain:
$ wget https://developer.arm.com/-/media/Files/downloads/gnu/11.2-2022.02/binrel/gcc-arm-11.2-2022.02-x86_64-arm-none-linux-gnueabihf.tar.xz
$ tar xf gcc-arm-11.2-2022.02-x86_64-arm-none-linux-gnueabihf.tar.xz
$ rm gcc-arm-11.2-2022.02-x86_64-arm-none-linux-gnueabihf.tar.xz
$ export PATH=`pwd`/gcc-arm-11.2-2022.02-x86_64-arm-none-linux-gnueabihf/bin:$PATH
$ export ARCH=arm
$ export CROSS_COMPILE=arm-none-linux-gnueabihf-
■ This article boots Linux from a boot loader; to boot Linux, you need the Linux kernel, the Linux device tree, and the Root Filesystem (RootFs). Please refer to the following related article for the procedure to create Linux binaries.
Note:
This article assumes that the following Linux binary files have already been generated under the $LINUX_BIN/a9 folder, as built in the related articles above.
Table 1. Linux binary files pre-built in the $LINUX_BIN/a9 folder
| File | Description |
| zImage | Compressed kernel image |
| socfpga_cyclone5_socdk.dtb | Device tree blob for both SD/MMC boot and QSPI boot for Cyclone® V SoCs |
| core-image-minimal-cyclone5.tar.gz | RootFs for Cyclone® V SoC (tar archive format) |
2-2. Building the Cyclone® V SoC Boot Loader (for SD card boot)
2-2-1. Setup
(1) Create a Top folder:
$ mkdir cv_example.sdmmc
$ cd cv_example.sdmmc
$ export TOP_FOLDER=`pwd`
(2) Get the hardware design from GitHub and compile it. Delete the already compiled software folder in it:
$ cd $TOP_FOLDER
$ rm -rf ghrd-socfpga-QPDS22.1STD_REL_GSRD_PR QPDS22.1STD_REL_GSRD_PR.zip cv_soc_devkit_ghrd
$ wget https://github.com/altera-opensource/ghrd-socfpga/archive/refs/tags/QPDS22.1STD_REL_GSRD_PR.zip
$ unzip QPDS22.1STD_REL_GSRD_PR.zip
$ mv ghrd-socfpga-QPDS22.1STD_REL_GSRD_PR/cv_soc_devkit_ghrd .
$ rm -rf ghrd-socfpga-QPDS22.1STD_REL_GSRD_PR QPDS22.1STD_REL_GSRD_PR.zip
$ cd cv_soc_devkit_ghrd
$ rm -rf software
$ ~/intelFPGA/22.1std/nios2eds/nios2_command_shell.sh \
make generate_from_tcl
$ ~/intelFPGA/22.1std/nios2eds/nios2_command_shell.sh \
make sof
2-2-2. Build U-Boot
(1) Clone the git tree and check out the supported branches to get the U-Boot source code:
$ cd $TOP_FOLDER/cv_soc_devkit_ghrd
$ mkdir software
$ mkdir software/bootloader
$ cd software/bootloader
$ git clone https://github.com/altera-opensource/u-boot-socfpga
$ cd u-boot-socfpga
# If you are using the latest U-Boot branch, comment out the following line
$ git checkout -b test-bootloader -t origin/socfpga_v2022.04
(2) Run the cv_bsp_generator.py script to get the sources from the handoff folder, format them appropriately, and copy them into the U-Boot source code:
$ cd $TOP_FOLDER/cv_soc_devkit_ghrd/software/bootloader/u-boot-socfpga/arch/arm/mach-socfpga/cv_bsp_generator
$ python cv_bsp_generator.py -i $TOP_FOLDER/cv_soc_devkit_ghrd/hps_isw_handoff/soc_system_hps_0 \
-o ../../../../board/altera/cyclone5-socdk/qts
(3) Configure and build U-Boot:
$ cd $TOP_FOLDER/cv_soc_devkit_ghrd/software/bootloader/u-boot-socfpga
$ export CROSS_COMPILE=arm-none-linux-gnueabihf-
$ make socfpga_cyclone5_defconfig
$ make -j 48
(4) The following files are built in the $TOP_FOLDER/cv_soc_devkit_ghrd/software/bootloader/u-boot-socfpga folder:
Table 2. Preloader (SPL) and U-Boot files generated by the build
| File | Description |
| spl/u-boot-spl | SPL ELF executable file |
| u-boot | U-Boot ELF executable |
| u-boot-with-spl.sfp | Bootable files: 4 copies of SPL and 1 copy on U-Boot image |
2-2-3. Prepare SD card image
(1) Create sd_card folder and get SD card script:
$ cd $TOP_FOLDER/
$ sudo rm -rf sd_card && mkdir sd_card && cd sd_card
$ wget https://releases.rocketboards.org/2021.04/gsrd/tools/make_sdimage_p3.py
$ chmod +x make_sdimage_p3.py
(2) Prepare a FAT partition:
$ cd $TOP_FOLDER/sd_card
$ mkdir sdfs && cd sdfs
$ export LINUX_BIN=~/linux-bin ← export the path to LINUX_BIN
$ cp $LINUX_BIN/a9/zImage .
$ cp $LINUX_BIN/a9/socfpga_cyclone5_socdk.dtb .
$ mkdir extlinux
$ echo "LABEL Linux Default" > extlinux/extlinux.conf
$ echo " KERNEL ../zImage" >> extlinux/extlinux.conf
$ echo " FDT ../socfpga_cyclone5_socdk.dtb" >> extlinux/extlinux.conf
$ echo " APPEND root=/dev/mmcblk0p2 rw rootwait earlyprintk console=ttyS0,115200n8" >> extlinux/extlinux.conf
(3) Prepare RootFs partition:
$ cd $TOP_FOLDER/sd_card
$ sudo rm -rf rootfs
$ mkdir rootfs && cd rootfs
$ sudo tar xf $LINUX_BIN/a9/core-image-minimal-cyclone5.tar.gz
$ sudo rm -rf lib/modules/*
$ sudo cp -r $LINUX_BIN/a9/modules/* lib/modules
(4) Copy the bootable binary file of U-boot:
$ cd $TOP_FOLDER/sd_card
$ cp ../cv_soc_devkit_ghrd/software/bootloader/u-boot-socfpga/u-boot-with-spl.sfp .
(5) Prepare SD card image:
$ cd $TOP_FOLDER/sd_card
$ sudo python3 ./make_sdimage_p3.py -f \
-P u-boot-with-spl.sfp,num=3,format=raw,size=10M,type=A2 \
-P sdfs/*,num=1,format=fat32,size=100M \
-P rootfs/*,num=2,format=ext3,size=300M \
-s 512M \ -n sdcard_cv
-n sdcard_cv.img
(6) Write the generated SD card image sdcard_cv.img to the SD card (using Win32DiskImager
or similar).
2-2-4. Booting from SD card
(1) Insert the SD card into the SD card slot of the Cyclone® V SoC Development Kit.
(2) Set the BSEL jumper so that the Cyclone® V SoC Development Kit boots from the 3.3V SD device:
-
-
- BSEL2 = 1 (left)
- BSEL1 = 0 (right)
- BSEL0 = 1 (left)
-
(3) Power on the Cyclone® V SoC Development Kit again to boot Linux. Log in without password using "root" as the user name:
U-Boot SPL 2022.04-21237-gfda0d9176f-dirty (Mar 16 2023 - 14:24:48 +0900)
DDRCAL: Scrubbing ECC RAM (1024 MiB).
DDRCAL: SDRAM-ECC initialized success with 578 ms
Trying to boot from MMC1
U-Boot 2022.04-21237-gfda0d9176f-dirty (Mar 16 2023 - 14:24:48 +0900)
CPU: Altera SoCFPGA Platform
FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0
BOOT: SD/MMC Internal Transceiver (3.0V)
Watchdog enabled
DRAM: 1 GiB
Core: 25 devices, 15 uclasses , devicetree: separate
MMC: dwmmc0@ff704000: 0
Loading Environment from MMC... *** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
Model: Altera SOCFPGA Cyclone V SoC Development Kit
Net:
Warning:. ethernet@ff702000 (eth0) using random MAC address - ca:ff:d4:a6:68:65
eth0: ethernet@ff702000
Hit any key to stop autoboot: 0
Failed to load 'u-boot. scr'
switch to partitions #0, OK
mmc0 is current device
Scanning mmc 0:1. .
Found /extlinux/extlinux.conf
Retrieving file: /extlinux/extlinux.conf
1: Linux Default
Retrieving file: /extlinux/.. /zImage
append: root=/dev/mmcblk0p2 rw rootwait earlyprintk console=ttyS0,115200n8
Retrieving file: /extlinux/.. /socfpga_cyclone5_socdk.dtb
Kernel image @ 0x1000000 [ 0x000000 - 0x55cbc0 ]
## Flattened Device Tree blob at 02000000
Booting using the fdt blob at 0x 2000000
Loading Device Tree to 09ff6000, end 09fffb91 ... OK
Starting kernel ... .
Deasserting all peripheral resets
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 5.15.70-153198-gf87aaa2c4d7c-dirty ( ubuntu@ubuntu1804) (arm-none-linux-gnueabihf-gcc (GNU Toolchain for the Arm Architecture 11.2-2022.02 (arm-11.14)) 11.2.1 20220111, GNU ld (GNU Toolchain for the Arm Architecture 11.2-2022.02 (arm-11.14)) 2.37.20220122) #1 SMP Tue Mar 14 09:48:08 JST 2023
[ 0.000000] CPU: ARMv7 Processor [413fc 090] revision 0 (ARMv7), cr=10c5387d
[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[ 0.000000] OF: fdt: Machine model: Altera SOCFPGA Cyclone V SoC Development Kit
- omitted in the middle -
[ 4.857493] socfpga-dwmac ff702000.ethernet eth0: No Safety Features support found
[ 4. 875296] socfpga-dwmac ff702000.ethernet eth0: registered PTP clock
[ 4.885533] socfpga-dwmac ff702000.ethernet eth0: configuring for phy/rgmii link mode
udhcpc: started, v1.34.1
udhcpc: broadcasting discover
udhcpc: broadcasting discover
udhcpc: broadcasting discover
udhcpc: no lease, forking to background done forking to background
done.
Starting syslogd/klogd: done
Poky (Yocto Project Reference Distro) 3.4.4 cyclone5 /dev/ttyS0
cyclone5 login: root
root@cyclone5:~#
Now we have confirmed that Linux boots with the generated boot loader for the SD card.
2-3. Building the Cyclone® V SoC Boot Loader (for QSPI boot)
2-3-1. Setup
(1) Create a Top folder:
$ mkdir cv_example.qspi
$ cd cv_example.qspi
$ export TOP_FOLDER=`pwd`
(2) Get the hardware design from GitHub and compile it. Delete the already compiled software folder in it:
$ cd $TOP_FOLDER
$ rm -rf ghrd-socfpga-QPDS22.1STD_REL_GSRD_PR QPDS22.1STD_REL_GSRD_PR.zip cv_soc_devkit_ghrd
$ wget https://github.com/altera-opensource/ghrd-socfpga/archive/refs/tags/QPDS22.1STD_REL_GSRD_PR.zip
$ unzip QPDS22.1STD_REL_GSRD_PR.zip
$ mv ghrd-socfpga-QPDS22.1STD_REL_GSRD_PR/cv_soc_devkit_ghrd .
$ rm -rf ghrd-socfpga-QPDS22.1STD_REL_GSRD_PR QPDS22.1STD_REL_GSRD_PR.zip
$ cd cv_soc_devkit_ghrd
$ rm -rf software
$ ~/intelFPGA/22.1std/nios2eds/nios2_command_shell.sh \
make generate_from_tcl
$ ~/intelFPGA/22.1std/nios2eds/nios2_command_shell.sh \
make sof
2-3-2. Build U-Boot
(1) Clone the git tree and check out the supported branches to get the U-Boot source code:
$ cd $TOP_FOLDER/cv_soc_devkit_ghrd
$ mkdir software
$ mkdir software/bootloader
$ cd software/bootloader
$ git clone https://github.com/altera-opensource/u-boot-socfpga
$ cd u-boot-socfpga
# If you are using the latest U-Boot branch, comment out the following line
# $ git checkout -b test-bootloader -t origin/socfpga_v2022.04
(2) Run the cv_bsp_generator.py script to get the sources from the handoff folder, format them appropriately, and copy them into the U-Boot source code:
$ cd $TOP_FOLDER/cv_soc_devkit_ghrd/software/bootloader/u-boot-socfpga/arch/arm/mach-socfpga/cv_bsp_generator
$ python cv_bsp_generator.py -i $TOP_FOLDER/cv_soc_devkit_ghrd/hps_isw_handoff/soc_system_hps_0 \
-o ../../../../board/altera/cyclone5-socdk/qts
(3) Configure and build U-Boot:
$ cd $TOP_FOLDER/cv_soc_devkit_ghrd/software/bootloader/u-boot-socfpga
$ export CROSS_COMPILE=arm-none-linux-gnueabihf-
$ make socfpga_cyclone5_qspi_defconfig
$ make -j 48
(4) The following files are built in the $TOP_FOLDER/cv_soc_devkit_ghrd/software/bootloader/u-boot-socfpga folder:
Table 3. Preloader (SPL) and U-Boot files generated by the build
| File | Description |
| spl/u-boot-spl | SPL ELF executable file |
| u-boot | U-Boot ELF executable |
| u-boot-with-spl.sfp | Bootable files: 4 copies of SPL and 1 copy on U-Boot image |
2-3-3. Prepare QSPI binaries
(1) Create a qspi_bin folder and import all files:
$ cd $TOP_FOLDER/
$ sudo rm -rf qspi_bin && mkdir qspi_bin && cd qspi_bin
$ cp ../cv_soc_devkit_ghrd/software/bootloader/u-boot-socfpga/u-boot-with-spl.sfp .
$ export LINUX_BIN=~/linux-bin ← export the path to LINUX_BIN
$ cp $LINUX_BIN/a9/zImage .
$ cp $LINUX_BIN/a9/socfpga_cyclone5_socdk.dtb .
(2) Build the RootFs JFFS2 image:
$ cd $TOP_FOLDER/qspi_bin
$ sudo rm -rf core-image-minimal-cyclone5-rootfs
$ mkdir core-image-minimal-cyclone5-rootfs
$ cd core-image-minimal-cyclone5-rootfs
$ sudo tar xf $LINUX_BIN/a9/core-image-minimal-cyclone5.tar.gz
$ sudo rm -rf lib/modules/*
$ cd ..
$ sudo apt install mtd-utils ← Install the packages required to run mkfs.jffs2
$ sudo mkfs.jffs2 -r core-image-minimal-cyclone5-rootfs -s 256 -e 64KiB --squash -o core-image-minimal-cyclone5-rootfs.jffs2
$ sudo chown $USER:$USER core-image-minimal-cyclone5-rootfs.jffs2
$ sudo rm -rf core-image-minimal-cyclone5-rootfs
(3) At this point, the following binaries are available in $TOP_FOLDER/qspi_bin:
Table 4. Files used for Linux boot
| File | Description |
| u-boot-with-spl.sfp | Four SPL images and U-Boot image |
| socfpga_cyclone5_socdk.dtb | Linux device tree blob |
| zImage | Compressed Linux kernel |
| core-image-minimal-cyclone5-rootfs.jffs2 | RootFs for Cyclone® V SoC (jffs2 format) |
2-3-4. Boot from QSPI
(1) Set the BSEL jumper so that the Cyclone® V SoC Development Kit boots from a 3.3V QSPI device:
-
-
- BSEL2 = 1 (left)
- BSEL1 = 1 (left)
- BSEL0 = 1 (left)
-
(2) Write the binary to the QSPI flash:
Table 5. Correspondence between file and address to be written to QSPI Flash
| Address | File | Description |
| 0x0000000 | u-boot-with-spl.sfp | U-Boot image with four SPL binaries |
| 0x0200000 | n/a | U-Boot environment |
| 0x0220000 | socfpga_cyclone5_socdk.dtb | Device tree blob for both SD/MMC boot and QSPI boot for Cyclone® V SoCs |
| 0x0230000 | zImage | Linux kernel |
| 0x0800000 | core-image-minimal-cyclone5-rootfs.jffs2 | RootFs for Cyclone® V SoC (jffs2 format) |
$ cd $TOP_FOLDER/qspi_bin
$ ~/intelFPGA/22.1std/nios2eds/nios2_command_shell.sh \
quartus_hps -c 1 -o pv -a 0x000000 u-boot-with-spl.sfp
$ ~/intelFPGA/22.1std/nios2eds/nios2_command_shell.sh \
quartus_hps -c 1 -o pv -a 0x220000 socfpga_cyclone5_socdk.dtb
$ ~/intelFPGA/22.1std/nios2eds/nios2_command_shell.sh \
quartus_hps -c 1 -o pv -a 0x230000 zImage
$ ~/intelFPGA/22.1std/nios2eds/nios2_command_shell.sh \
quartus_hps -c 1 -o pv -a 0x800000 -s 0x3800000 core-image-minimal-cyclone5-rootfs.jffs2
(3) Power on the Cyclone® V SoC Development Kit again and boot Linux. Log in without password, using "root" as the user name:
U-Boot SPL 2022.04-21237-gfda0d9176f-dirty (Mar 20 2023 - 18:57:25 +0900)
DDRCAL: Scrubbing ECC RAM (1024 MiB).
DDRCAL: SDRAM-ECC initialized success with 579 ms
Trying to boot from SPI
U-Boot 2022.04-21237-gfda0d9176f-dirty (Mar 20 2023 - 18:57:25 +0900)
CPU: Altera SoCFPGA Platform
FPGA:. Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0
BOOT: QSPI Flash (3.0V)
Watchdog enabled
DRAM: 1 GiB
Core: 25 devices, 15 uclasses, devicetree: separate
MMC: dwmmc0@ff704000: 0
Loading Environment from SPIFlash... SF: Detected n25q512ax3 with page size 256 Bytes, erase size 64 KiB, total 64 MiB
*** Warning - bad CRC, using default environment
In: serial
Out: serial
Err : serial
Model: Altera SOCFPGA Cyclone V SoC Development Kit
Net:
Warning: ethernet@ff702000 (eth0) using random MAC address - 36:3f:43:8c:6c:0b
eth0: ethernet@ff702000
Hit any key to stop autoboot: 0
SF: Detected n25q512ax3 with page size 256 Bytes, erase size 64 KiB, total 64 MiB
device 0 offset 0x230000 , size 0x5d0000
SF: 6094848 bytes @ 0x230000 Read: OK
device 0 offset 0x220000, size 0x10000
SF: 65536 bytes @ 0x220000 Read: OK
Kernel image @ 0x1000000 [ 0x 000000 - 0x55cbc0 ]
## Flattened Device Tree blob at 02000000
Booting using the fdt blob at 0x2000000
Loading Device Tree to 09ff6000, end 09fffb91 ... OK
Starting kernel ... .
Deasserting all peripheral resets
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 5.15.70-153198-gf87aaa2c4d7c-dirty ( ubuntu@ubuntu1804) (arm-none-linux-gnueabihf-gcc (GNU Toolchain for the Arm Architecture 11.2-2022.02 (arm-11.14)) 11.2.1 20220111, GNU ld (GNU Toolchain for the Arm Architecture 11.2-2022.02 (arm-11.14)) 2.37.20220122) #1 SMP Tue Mar 14 09:48:08 JST 2023
[ 0.000000] CPU: ARMv7 Processor [413fc 090] revision 0 (ARMv7), cr=10c5387d
[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[ 0.000000] OF: fdt: Machine model: Altera SOCFPGA Cyclone V SoC Development Kit
- omitted in the middle -
[ 5.284680] socfpga-dwmac ff702000.ethernet eth0: No Safety Features support found
[ 5. 292635] socfpga-dwmac ff702000.ethernet eth0: registered PTP clock
[ 5.302575] socfpga-dwmac ff702000.ethernet eth0: configuring for phy/rgmii link mode
Poky (Yocto Project Reference Distro) 3.4.4 cyclone5 /dev/ttyS0
cyclone5 login: root
root@cyclone5:~#
Now we have confirmed that Linux boots with the generated boot loader for QSPI.
Conclusion
This article described the old and new bootloader build flow for the Cyclone® V SoC and Arria® V SoC cases, as well as the steps to build a bootloader on the Cyclone® V SoC.
We hope this will be helpful for bootloader generation.