This article provides notes on designing for boards with SoC FPGAs using Quartus® Prime development software (" Quartus® ") and specifying the pinout on the HPS side.
Introduction
Quartus® designs targeting SoC FPGA devices generally do not require HPS-side pin location assignments. The HPS-side pin assignments are automatically determined by Quartus® based on the user-specified HPS component option settings in the Platform Designer.
On the other hand, the Assignment Editor also allows the user to specify the location assignment of the HPS-side pins, which can cause problems if incorrect locations are specified.
This section introduces some points (points to note) to avoid unnecessary trouble when HPS-side pin location assignments are made on a Quartus® design.
Tip: This does not apply when routing the pins of the peripheral controller built into the HPS to the FPGA side; the pin assignments of the signal lines routed to the FPGA side must be set individually in the Assignment Editor (or in a file with a .qsf extension).
1. Troubleshooting Points
Basically, the 'HPS' pin assignment is the same as the 'HPS' pin assignment in the FPGA. Do not perform HPS pin location assignment. This is the most effective countermeasure.
However, there may be cases in which incorrect assignments are unintentionally mixed in, The following are points to be aware of unintentional mix-ups.
The response of Quartus® to HPS pin location assignments seems to vary by device family. Therefore, the points to be aware of will also vary from family to family.
|
Device Family |
Warnings from Quartus® (compile-time messages and results) | Need for Attention |
| V Series ( Cyclone® V SoC / Arria® V SoC) |
No message displayed. Compilation completed successfully. |
Caution required! |
| Arria® 10 SoC |
Critical Warning. Compilation error. |
Not Required |
| Stratix® 10 SoC |
Critical Warning is displayed. Compilation completed successfully. |
Caution required! |
2. Points to check by device family
Based on the warning from Quartus® described above, here are the check points for each device family to notice incorrect location assignments for the HPS pins.
2-1. V Series ( Cyclone® V SoC / Arria® V SoC)
Check the Ignored Assignments in the Fitter Report when compilation is completed.
If a location assignment is specified for the pins on the HPS side, a report of "HPS_LOCATION" will appear in the Ignored Assignments list of the Fitter Report, regardless of whether the specified location is correct or incorrect. (It is an Ignored list, but it does not seem to ignore it completely.)
Please take action so that there is no "HPS_LOCATION" report in the Ignored Assignments list.
Figure 1. Example of the "HPS_LOCATION" report on the Ignored Assignments list
2-2. Arria® 10 SoC
There is no point to be checked separately because a compile (Fitter) error occurs.
Although it is not a point to be checked during compilation, when creating a design based on the "GHRD (Golden Hardware Reference Design)", a hardware reference design for the Arria® 10 SoC Development Kit, it is recommended to check the location assignment of all the HPS pins in advance. Note that when creating a design based on the Golden Hardware Reference Design (GHRD) for the Arria® 10 SoC Development Kit, the location assignments for all HPS pins are specified in advance.
Tip: The location assignments need to be changed appropriately, but if the change is too time-consuming, deleting the location assignments for the HPS pins may be acceptable. (Deleting it may be recommended to reduce the possibility of setting errors.)
2-3. Stratix® 10 SoC
Check the critical warning in Messages of the Fitter Report when the compilation is completed.
If an incorrect location assignment is specified for a pin on the HPS side, the message "Found LOCATION assignments found for "xxxx" pin with multiple values. (Message ID 16643)" critical warning. (No message for correct location assignment).
Please take measures to eliminate the critical warning Message ID 16643.
Figure 2. Example of displaying critical warning for Message ID 16643
Summary
The contents of this article were verified with the latest Quartus® (v19.1 Standard / v19.4 Pro), which is currently being released, but even in past versions, the pin assignments on the HPS side basically do not need to be specified. Therefore, if incorrect location assignments are mixed in with the HPS-side pins, it may be difficult to notice the problem, and it may take a long time to investigate.
When you create a design for a board with an SoC FPGA, we recommend that you check the points described in this article before you verify the design on the actual device.
Links to related articles
Please refer to the following article for the Hard Processor System External Memory Interface (HPS EMIF) pin connection limitations of the Stratix® 10 SoC and Arria® 10 SoC:
Reference: Schematic Checklist for Stratix® 10 SoC and Arria® 10 SoC HPS EMIF - (In Japanese)