Introduction
The internal resistance (ODT: On Die Termination) of SDRAM must be set for EMIF (External Memory Interface) IP.
The following three settings can be configured in the "Memory I/O Settings" in the "Mem I/O" tab.
- Output drive strength settings
- Dynamic ODT (Rtt_WR) value
- ODT Rtt nominal value
Figure 1. Memory I/O" tab with three settings
The optimal ODT value is set based on the board simulation results, but by using Intel's EMIF Toolkit functionality, the optimal ODT value for the board can be confirmed on the actual board.
This article describes how to check the optimal ODT value on the actual board and how to reflect the value in the IP.
- Target device: Intel® Altera® 10 FPGA
- Target memory topology: DDR4, DDR3
This article uses the EMIF Toolkit, so it is necessary to have a board on which the EMIF IP actually runs on the FPGA. Board that actually runs EMIF IP in FPGA is required for this article.
Obtaining optimal ODT values with the EMIF Toolkit
To obtain the optimal ODT values for SDRAM, the EMIF Toolkit must be running on the target board. First, please make sure that the EMIF Toolkit operates on the target board.
Please refer to the following document for the specific connection procedure of EMIF Toolkit.
Reference document:
EMIF Design & Debug Guidelines for FPGAs
- https://www.macnica.co.jp/en/business/semiconductor/articles/intel/129749/
-
"Design & Debug Guidelines (Rev. 3.2) / Arria® 10 Edition" (Japanese document Link)
- Appendix : How to use the EMIF ToolKit
Once the EMIF Toolkit is ready, click on "Calibrate Termination" in the Tasks window to perform the calibration for the ODT.
Figure 2. Calibrate Termination" in the Tasks window
The obtained optimal ODT value is reflected in the EMIF IP
When "Calibrate Termination" is completed, the following three results are displayed from the "Calibrate Termination Report".
Figure 3. Obtained On-Die Termination
Figure 4. Obtained Dynamic On-Die Termination
Figure 5. Obtained Output Drive Strength
The setting with the highest margin in each result (red frame above) is the optimal ODT value.
The optimal ODT value is the one with the highest Margin (red box above).
Figure 6. IP settings at the time of measurement and values to be changed
Memo:
The "Memory I/O Settings" setting name on the EMIF IP Settings screen and the "Calibrate Termination Report" display name are different, and the table below describes the differences.
| Memory I/O Settings | Calibrate Termination Report |
| Output drive strength setting | Output Drive Strength |
| Dynamic ODT (Rtt_WR) value | Dynamic On-Die Termination |
| ODT Rtt nominal value | On-Die Termination |
Table 1. Comparison of "Memory I/O Settings" and "Calibrate Termination Report" display
Result of changing ODT value
The ODT value was changed, recompiled, and written to the FPGA again.
After that, EMIF Toolkit is started and "Calibrate Termination" is executed again.
The "Calibrate Termination Report" produced the following results.
Figure 7. On-Die Termination with optimal values
Figure 8. Optimal Dynamic On-Die Termination
Figure 9. Optimal Output Drive Strength
Optimal Output Drive Strength (ODT) values were set to ensure maximum margin for all settings.
Figure 10. Maximum margin was secured by changing the ODT value.
Conclusion
In this article, we introduced how to check the optimal ODT value on the actual board and how to reflect the value in the IP.
By setting the optimal ODT value to the EMIF IP, the appropriate ODT will be set for the target board, so why not give it a try?
Notes:
The Margin value is a result of the conditions (temperature, voltage, etc.) at the time of Calibrate Termination, so the Margin value may change each time it is performed.