Introduction.
This is an example of timing constraints for a system connection in which the output from the FPGA is latched by an external clock.
Please refer to this example as a support for your understanding only, rather than copying the SDC from this example, because the SDC is a reasonable constraint to set considering the system configuration, RTL, and your specifications.
This content explains the concept of timing constraints for FPGA output pins and how to check Timing Analyzer reports.
System Configuration
This example shows a case where data output from the FPGA is latched by an external clock of an external IC.
SDC Constraints
If no board delays are taken into account, an example of timing constraints is shown below.
Clock constraint to synchronize the last-stage FF (Launch Clock)
create_clock -name CLK_50M -period 20.000 [get_ports {CLK_50M}]]
Virtual clock constraint for external clock to synchronize FF of receiving device (Latch Clock)
create_clock -name CLK_50M_vir -period 20.000
set_output_delay constraint for Port of DATAOUT
set_output_delay -clock { CLK_50M_vir } -max -add_delay 3.000 [get_ports {DATAOUT}]]
set_output_delay -clock { CLK_50M_vir } -min -add_delay -1.000 [get_ports {DATAOUT}]]
Note that the value of -min is - (minus) when Th is held from the latch clock.
Check Report Timing
After compiling with timing constraints, check the results of the constraints with Timing Analyzer by following the steps below.
Create a netlist for timing analysis in Timing Analyzer .
Open the Report Timing setting screen,
Open the Report Timing Settings screen and set the SDC results to be reported as shown in the figure below (Figure 4).
In the setup analysis of Report Timing, the value set by -max is taken into account.
In the hold analysis of Report Timing, the value set by -min is taken into account.
This completes the output constraints and checks for latching with an external clock.
Please refer to the above for further reference.