Intel® Stratix® 10 Device Design Guidelines Supplement

* The original content was created in Japanese, so some information, images, and links may still be in Japanese. We’re updating gradually and appreciate your patience.

Introduction

In order to establish a high-density, high-performance Stratix^® 10 design, it is important to plan the FPGA and system early in the design process.

The Intel® Stratix^® 10 Device Design Guidelines provide design guidelines for each stage of the design flow to increase productivity and avoid common design pitfalls.

Intel® Stratix^® 10 Device Design Guidelines

• https://www.intel.com/content/www/us/en/docs/programmable/683738/current/device-design-guidelines.html

This document is a supplement to the "Design Guidelines for Intel® Stratix^® 10 Device evices" that summarizes key points to be aware of. It is not a complete list of design stage considerations and should be used in conjunction with the "Design Guidelines for Intel® Stratix^® 10 Devices" document.

Contents

1. Device Variations
2. Power Supply Design
3. Thermal Design
4. Configuration
5. Debugging with SDM Debugger

<Appendix>

1. Automatic JTAG clock frequency setting
2. Configuration settings
3. Device Variations

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Intel® Stratix® 10 Device Design Guidelines Supplement (Japanese)