1. Introduction
The design example attached to this article is an example of controlling an MAX® 10 ADC (A/D converter) written in Verilog HDL or VHDL.
This is a useful design example for hardware designers who want to control the ADC using only hardware logic, without using a microcontroller.
Although a dedicated IP core is used to control the MAX® ADC, this design example provides an example description up to the point where digital data is obtained from the ADC by specifying commands and channel numbers.
2. Advantages of Using This Example
- Control the MAX® 10 ADC with only hardware knowledge
- No software knowledge is required since the Nios® II Processor and Platform Designer (formerly Qsys) are not used
- Samples can be used as a reference for design applications
Reference:
For ADC-related content on MAX® 10, please also see the following content (Japanese)
3. environment for use
The following development tools are used in this article.
Table 1 Development tools used in this article
| Item No. | Item | Description |
| 1 | Quartus® Prime Development Software Standard Edition (hereafter referred to as Quartus® Prime) | A tool for developing FPGA hardware. This document uses Quartus® Prime Development Software Standard Edition v18.1. |
| 2 | Modular ADC core IP | This IP core can be used to control the ADC embedded in MAX® 10 FPGAs. In this article, it will be referred to as the ADC IP core. |
4. Features of this sample
4-1. ADC IP Core
The configuration and settings of the ADC IP core in this sample are as follows.
- Configured in the simplest ADC_control_core_only mode (see Figure 1)
- Set the input clock to 10 MHz
- Set ADC sampling rate to 1MHz
- Set analog input channels to 9 (CH0 ~ CH8) Temperature sensor diode (TSD) is not set (see Figure 2)
Point:
input clock is divided on the ADC side to match the specified sampling rate.
Tip:
The combination of input clock and sampling rate is defined and must be known in advance. Details can be found in the following documents
MAX® 10 Analog to Digital Converter User Guide
(search for Valid ADC Sample Rate and Input Clock Combination)
Figure 1 ADC IP Settings Screen
Figure 2 Channel Settings Screen
4-2. Control Logic
In this sample, the following control is performed by issuing commands to the ADC IP core.
- Control for 8 input channels
- CH0 ~ CH7
- Sequence of channels is specified in order of number.
- CH0 (1st) ➡ CH1 ➡ ... ➡ CH6 ➡ CH7 (8th) ➡ CH0 (1st) ➡ ...
- Fix start of packet and end of packet to '0' since they are ignored inside ADC
4-3. target evaluation board
This sample uses the MAX® 10 FPGA Evaluation Kit to verify the operation.
5. sample project
Sample projects (Verilog HDL / VHDL) for the example designs shown on this page are attached.