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How to set/check EMIF Debug Report for HPS block

How to set/check EMIF Debug Report for HPS block

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Introduction

The SDRAM Controller in the Hard Processor System (HPS) of the Arria® V SoC and Cyclone® V SoC does not support the EMIF Debug Toolkit or EMIF On-Ship Debug Port.

For this reason, we will show you how to get the HPS to output debug reports.

This technical content is based on the following URL

 

Setting up to output the HPS debug report

You can output the debug report by the following procedure.

  1. Open <design_name>/hps_isw_handoff/sequencer_defines.h in a text editor.
  2. Move to #define RUNTIME_CAL_REPORT 0 in sequencer_defines.h
  3. Change #define RUNTIME_CAL_REPORT 0 to #define RUNTIME_CAL_REPORT 1 and save
  4. Set semihosting to Enabled or UART output to generate board support package (BSP)

This setting will cause the system to output a debug report including the calibration process.

 

How to read/check the debug report

The following is an explanation of the items listed in the debug report.

The following explanation uses the results of the attached " HPS_emif_debug_report.txt " as an example.

 

Results of VFIFO and Delay settings for each DQS group

For the DQS Enable group, the VFIFO setting (1 clock cycle), the number of Phase Taps (1/8 clock cycle), and the number of Delay Chain steps (every 25 ps) can be checked.

The width of DQS Enable is indicated by the difference between the Start and End positions.

 C: DQS Enable ; Group 0 ; Rank 0 ; Start VFIFO 5 ; Phase 5 ; Delay 7 
SEQ.C: DQS Enable ; Group 0 ; Rank 0 ; End VFIFO 6 ; Phase 5 ; Delay 0 
SEQ. Rank 0 ; Center VFIFO 6 ; Phase 1 ; Delay 4

In the above example, DDR clock = 333MHz (3000ps)

Start : 5 x 3000 + (5 x 3000)/8 + 7 x 25 = 17,050ps

End : 6 x 3000 + (5 x 3000)/8 + 0 x 25 = 19,875ps

Therefore, the width of DQS Enable is 2,825ps (= 19,875 - 17,050).

 

Results of Write Deskew, Read Deskew, DM Deskew, and Read after Write for each DQ group

The values of Write Deskew, Read Deskew, DM Deskew, and Read after Write are Delay Step values, and 1 Step is 25 ps in the Arria® V / Cyclone® V series.

 C: Read Deskew ; DQ 0 ; Rank 0 ; Left edge 23 ; Right edge 27 ; DQ delay 2 ; DQS delay 8

In this example, DQ0 is located 23 steps from the center (DQS edge) to the left edge (Left edge) and 27 steps to the right edge (Right edge).

One step (delay chain step size) is 25ps, so 
(left edge + right edge) * delay chain step size = (23 + 27) * 25ps = 1250ps DQ0 is open at the width of 
.

 

Checking for Calibration Success/Failure

In this example

 SEQ.C: Calibration Passed

C: Calibration Passed" indicates that the calibration has passed.

 

What to do if Calibration fails

If the calibration fails, please check the log as follows

 SEQ.C: Calibration Failed 
SEQ.C: Error Stage : <Num> 
SEQ.C: Error Substage: <Num> 
SEQ.C: Error Group : <Num>

You can see "which Stage/Substage" and "which Group" of Calibration failed.

Based on this information, you can refer to the document "EMIF Design & Debugging

EMIF Design & Debug Guidelines

Based on this information, set up and address the check items for each Stage described from page 23 (When Calibration Fails) to page 33 of the document "EMIF Design & Debug Guidelines" available at the following URL: .

 

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