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What to do when access to QSPI from HPS Flash Programmer is disabled

What to do when access to QSPI from HPS Flash Programmer is disabled

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Introduction

It is common practice to boot a hard processor system (HPS) from QSPI flash memory (QSPI) using a Cyclone® V SoC FPGA. In this case, if incorrect data is written to the QSPI, the HPS Flash Programmer (quartus_hps) may not be able to access the QSPI.

There are various reasons for this, but here are a few solutions.

* HPS = Hard Processor System

 

1. Try adding more options to the HPS Flash Programmer

HPS Flash Programmer has several options. Please try adding the following options first to see if you can recover.

$ quartus_hps -c 1 --boot=16 -o EB -a 0x0 -s 0x40000

 

As shown above, boot options are provided to specify, for example, to issue a Cold Reset before accessing the system. The following is the help description for v18.1.

__.png Note:
　* Option numbers may differ depending on the version.
　* Basically, we recommend using the latest version of the tool.

Also, the Intel® FPGA Download Cable II (formerly USB-Blaster II) has an additional reset pin for SoC devices. It is recommended to connect this pin to the nRST signal of the HPS, so please be careful when making the board.

__.png Reference: Intel® FPGA Download Cable II User Guide

Pin Active Serial (AS) Mode Passive Serial (PS) Mode JTAG Mode
Signal Name Description Signal Name Description Signal Name Description
1 DCLK Configuration Clock DCLK Configuration Clock TCK Test Clock
2 GND Signal ground GND Signal ground GND Signal ground
3 CONF_DONE Configuration done CONF_DONE Configuration done TDO Test Data Output
4 VCC(TRGT) Target power supply VCC(TRGT) Target power supply VCC(TRGT) Target power supply
5 nCONFIG Configuration control nCONFIG Configuration control TMS Test Mode Select Input
6 nCE Target chip enable - - PROC_RST Processor Reset
7 DATAOUT Active serial data out nSTATUS Configuration Status - -
8 nCS Serial configuration device chip select nCS Serial configuration device chip select - -
9 ASDI Active serial data in DATA0 Passive serial data in TDI Test Data Input
10 GND Signal ground GND Signal ground GND Signal ground

Note: Use pin 6 for hard processor reset under JTAG mode.
Note: The following note below only applies to Intel® Arria® 10 and earlier SoC devices. PROC_RST is not  used for Intel® Stratix® 10 SoC devices.
In JTAG mode, the PROC_RST pin can be used to trigger warm reset of the HPS block when prompted via the ARM DS-5 debugger. PROC_RST is an active low signal and not an open collector pin. As such, it is not recommended to connect PROC_RST to HPS_nRST directly. You should instead connect this pin to a secondary device such as the MAX V CPLD, and use the device to manage the reset network for HPS.

 

2. Run U-Boot from Arm® Development Studio 5 Intel® SoC FPGA  Edition to erase QSPI contents.

If the BSEL (Boot SEL) pin can be changed on the board, you can specify a pin other than QSPI so that the board will not boot with data that has been accidentally written. In this case, since access from JTAG is possible, it can be restored by using Arm® Development Studio 5 Intel® SoC FPGA Edition (DS-5) to start U-Boot and erase the contents of QSPI with the U-Boot command.

Please refer to the following page for information on how to start U-Boot from DS-5 and how to write to QSPI from U-Boot.

__.png Reference: How to start U-Boot with DS-5 - (In Japanese)

__.png Reference: How to write to QSPI with U-Boot - (In Japanese)

 

After U-Boot starts, try executing the sf command.

SOCFPGA_CYCLONE5 # sf 
sf - SPI flash sub-system 

Usage: 
sf probe [[bus:]cs] [hz] [mode] - init flash device on given SPI bus 
                                  and chip select 
sf read addr offset len - read `len' bytes starting at 
                          `offset' to memory at `addr' 
sf write addr offset len - write `len' bytes from memory 
                           at `addr' to flash at `offset' 
sf erase offset [+]len - erase `len' bytes from `offset' 
                         `+len' round up `len' to block size 
sf update addr offset len - erase and write `len' bytes from memory 
                            at `addr' to flash at `offset' 
SOCFPGA_CYCLONE5 #

The following is an example of deleting the Preloader area.

sf probe 
sf erase 0 40000

 

Other various techniques for DS-5 can be found below.

__.png Reference: Macnica's website : Arm DS utilization page

 

3. Change the TCK frequency of USB-Blaster

It is often the case that the JTAG signal quality is a problem and cannot be accessed properly. In such cases, try changing the TCK frequency by referring to the following article.

To change the frequency to 16MHz, execute the following command.

$ jtagconfig --setparam 1 JtagClock 16M

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