Introduction
If your RTL design includes a state machine description, you can change the encoding style of the state machine in the Intel® Quartus® Prime development software.
How to configure settings in Quartus® Prime
(1) Open Project...
Select File menu -> Open Project. Select File menu -> Open Project....
(2) Change settings
Select Assignments menu -> Settings.... Select Assignments menu -> Settings.
Select "Compiler Settings" from "Category:" and click the "Advanced Settings(Synthesis)" button.
State Machine Encoding Style Settings
The Synthesis settings window appears.
In the "Name:" field, there is a "State Machine Processing" setting that allows you to change the encoding style of the state machine.
The settings are Auto, Gray, Johnson, Minimal Bits, One-Hot, or User-Encoded.
If Auto is selected, it is set to One-Hot for FPGAs.
If the state bits of the state machine are specified in the description, select User-Encoded.
Setting up the Illegal State Processing Circuit
Even with an illegal state description, the circuit may not be optimized to generate all of the illegal processing circuits.
(This is true for any logic synthesis tool.)
To generate all the illigal processing circuits, select "Safe State Machine" from the "Name:" field and set "Setting:" to "On".
However, be aware that if a circuit generates a state machine with a large number of illegal states, especially if the state machine encoding style setting (State Machine Processing setting) is left set to One-Hot or Auto, the number of illegal state processing circuits will be huge. Be aware that the number of circuits for illegal state processing can be very large.
If the "Safe State Machine" setting is "On", it is recommended that the"State Machine Processing" setting be set to "User-Encoded" (or "Minimal Bits").
Note that setting to "Minimal Bits" has the disadvantage that the synthesized logic becomes more complex and the path becomes longer, which affects the timing.