Getting Started
We have noticed that building the Cyclone® V SoC FPGA Preloader on Windows® 10 often results in build errors. This seems to be due to the fact that Windows 10 natively supports the tar command.
Reference: https://forest.watch.impress.co.jp/docs/news/1097996.html - (In Japanese)
This causes the tar command used to build Preloader from Embedded_Command_Shell to be the tar command natively supported by Windows 10, and the tar command fails due to the difference in path concepts between Windows and UNIX systems.
[runtime error].
tar zxf /cygdrive/c/intelFPGA/18.1/embedded/host_tools/altera/preloader/uboot-socfpga.tar.gz
tar: Error opening archive: Failed to open '/cygdrive/c/intelFPGA/18.1/embedded/host_tools/altera/preloader/uboot-socfpga.tar.gz'
make: *** [uboot-socfpga/.untar] Error 1
This page describes countermeasures.
Countermeasures for each project
When you generate a project for Preloader in Preloader Generator (bsp-editor), a Makefile is generated.
Find line 93 of this Makefile and add the following bold line. This will use the tar commands included in the SoC FPGA Embedded Development Suite (SoC EDS).
ifeq ($(HOSTOS),cygwin)
UNTAR := $(SOCEDS_DEST_ROOT)/host_tools/cygwin/bin/tar zxf
Permanent measures
Since the above measures require editing each time, edit the data itself, which is the source of the Makefile generated by the Preloader Generator (bsp-editor). The relevant file is below. Edit it in the same way (it is recommended to copy and save the original file).
C:\intelFPGA\18.1\embedded\ip\altera\preloader\src\Makefile.template
ifeq ($(HOSTOS),cygwin)
UNTAR := $(SOCEDS_DEST_ROOT)/host_tools/cygwin/bin/tar zxf
If this does not work
Try editing the following file (please reboot after this edit):
C:\intelFPGA\18.1\embedded\host_tools\cygwin\etc\fstab
# /etc/fstab
#
# This file is read once by the first process in a Cygwin process tree.
# To pick up changes, restart all Cygwin processes. For a description
# see https://cygwin.com/cygwin-ug-net/using.html#mount-table
# This is default anyway:
#none /cygdrive cygdrive binary,posix=0,user 0 0
none / cygdrive cygdrive binary,posix=0,user,noacl 0 0
Reference information
The manufacturer has also released a countermeasure to this problem. Although the approach is slightly different, build errors can be avoided in this way as well.
References FPGA Knowledge Base - Unable to make preloader in Windows 10
Other reference information
Reference: SoC Beginner's Guide - Bare Metal Application Debugging with DS-5 - (In Japanese)
Reference: Beginner's Guide to SoC - How to use Preloader Generator - (In Japanese)